minor update

hw/rtl/libs/VX_onehot_encoder.v

@@ -6,7 +6,7 @@
 module VX_onehot_encoder #(
     parameter N       = 1,    
     parameter REVERSE = 0,
-    parameter FAST    = 1,
+    parameter MODEL   = 1,
     parameter LN      = `LOG2UP(N)
 ) (
     input wire [N-1:0]   data_in,    
@@ -23,7 +23,7 @@ module VX_onehot_encoder #(
         assign data_out  = data_in[!REVERSE];
         assign valid_out = (| data_in);
 
-    end else if (FAST) begin
+    end else if (MODEL == 1) begin
     `IGNORE_WARNINGS_BEGIN
         localparam levels_lp = $clog2(N);
         localparam aligned_width_lp = 1 << $clog2(N);
@@ -62,7 +62,22 @@ module VX_onehot_encoder #(
         assign data_out = addr[levels_lp][`LOG2UP(N)-1:0];
         assign valid_out = v[levels_lp][0];
     `IGNORE_WARNINGS_END
-    end else begin 
+    end else if (MODEL == 2) begin 
+
+        for (genvar j = 0; j < LN; ++j) begin
+            wire [N-1:0] mask;
+            for (genvar i = 0; i < N; ++i) begin
+            `IGNORE_WARNINGS_BEGIN
+                wire [LN-1:0] i_w = i;
+            `IGNORE_WARNINGS_END
+                assign mask[i] = i_w[j];
+            end
+            assign data_out[j] = |(mask & data_in);
+        end
+
+        assign valid_out = (| data_in);
+
+    end else begin
 
         reg [LN-1:0] index_r;