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Passing some cases

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This commit is contained in:
felsabbagh3
2020-03-04 04:05:54 -08:00
parent d8e25045be
commit aa1a0ee376
22 changed files with 217 additions and 153 deletions
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2
rtl/Makefile
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@@ -9,7 +9,7 @@ EXE=--exe ./simulate/test_bench.cpp
COMP=--compiler gcc
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO=
# LIGHTW=

33
rtl/VX_cache/VX_bank.v
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@@ -18,6 +18,7 @@ module VX_bank (
// Output Core WB
input wire bank_wb_pop,
output wire bank_wb_valid,
output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
@@ -78,7 +79,7 @@ module VX_bank (
assign reqq_push = !delay_req && (|bank_valids);
VX_cache_req_queue mrvq_queue(
VX_cache_req_queue req_queue(
.clk (clk),
.reset (reset),
// Enqueue
@@ -142,11 +143,11 @@ module VX_bank (
.miss_add_warp_num (miss_add_warp_num),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_resrv_full (mrvq_full)
.miss_resrv_full (mrvq_full),
// Broadcast
.is_fill_st1 (is_fill_st1),
.fill_addr_st1 (addr_st1[0]),
.is_fill_st1 (is_fill_st2),
.fill_addr_st1 (addr_st2),
// Dequeue
.miss_resrv_pop (mrvq_pop),
@@ -201,7 +202,7 @@ module VX_bank (
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 (
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -213,7 +214,7 @@ module VX_bank (
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc (
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -245,7 +246,7 @@ module VX_bank (
VX_tag_data_access VX_tag_data_access(
.clk (clk),
.reset (reset),
.stall (stall),
.stall (stall_bank_pipe),
// Initial Read
.readaddr_st10 (addr_st1[0]),
@@ -279,14 +280,15 @@ module VX_bank (
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
wire is_fill_st2;
VX_generic_register #(.N( 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 (
VX_generic_register #(.N( 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}),
.out ({valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
.in ({is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}),
.out ({is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
@@ -307,6 +309,7 @@ module VX_bank (
wire cwbq_full;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
@@ -322,13 +325,17 @@ module VX_bank (
// Enqueue to DWB Queue
wire dwbq_push = valid_st2 && miss_st2 && dirty_st2;
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]};
wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire dwbq_full;
// Enqueu in dram_fill_req
assign dram_fill_req = valid_st2 && miss_st2;
assign dram_fill_req_addr = addr_st2;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),
@@ -342,7 +349,7 @@ module VX_bank (
);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full);
endmodule

16
rtl/VX_cache/VX_cache.v
View File

@@ -45,6 +45,7 @@ module VX_cache (
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
wire [`NUMBER_BANKS-1:0] per_bank_wb_valid;
wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
@@ -60,14 +61,14 @@ module VX_cache (
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
wire[`NUMBER_BANKS-1:0] per_bank_reqq_full;
assign delay_req = (|per_bank_reqq_full);
assign dram_fill_accept = (`NUMBER_BANKS == 1) ? dram_fill_accept[0] : dram_fill_accept[dram_fill_addr[`BANK_SELECT_ADDR_RNG]];
assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
VX_cache_dram_req_arb VX_cache_dram_req_arb(
.clk (clk),
@@ -88,7 +89,7 @@ module VX_cache (
);
VX_cache_core_req_bank_sel VX_cache_core_req_bank_sel(
VX_cache_core_req_bank_sel VX_cache_core_req_bank_sell(
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids(per_bank_valids)
@@ -96,6 +97,7 @@ module VX_cache (
VX_cache_wb_sel_merge VX_cache_core_req_bank_sel(
.per_bank_wb_valid (per_bank_wb_valid),
.per_bank_wb_tid (per_bank_wb_tid),
.per_bank_wb_rd (per_bank_wb_rd),
.per_bank_wb_wb (per_bank_wb_wb),
@@ -103,6 +105,7 @@ module VX_cache (
.per_bank_wb_data (per_bank_wb_data),
.per_bank_wb_pop (per_bank_wb_pop),
.core_no_wb_slot (core_no_wb_slot),
.core_wb_valid (core_wb_valid),
.core_wb_req_rd (core_wb_req_rd),
.core_wb_req_wb (core_wb_req_wb),
@@ -110,8 +113,8 @@ module VX_cache (
.core_wb_readdata (core_wb_readdata)
);
genvar curr_bank;
generate
integer curr_bank;
for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
@@ -123,6 +126,7 @@ module VX_cache (
wire [2:0] curr_bank_mem_write;
wire curr_bank_wb_pop;
wire curr_bank_wb_valid;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
@@ -158,6 +162,7 @@ module VX_cache (
// Core WB
assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
assign per_bank_wb_valid [curr_bank] = curr_bank_wb_valid;
assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid;
assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd;
assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb;
@@ -170,7 +175,7 @@ module VX_cache (
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept;
@@ -199,6 +204,7 @@ module VX_cache (
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
.bank_wb_valid (curr_bank_wb_valid),
.bank_wb_tid (curr_bank_wb_tid),
.bank_wb_rd (curr_bank_wb_rd),
.bank_wb_wb (curr_bank_wb_wb),

96
rtl/VX_cache/VX_cache_config.v
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@@ -1,8 +1,10 @@
`include "../VX_define.h"
`include "../VX_define.v"
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
// ========================================= Configurable Knobs =========================================
// General Cache Knobs
@@ -42,45 +44,46 @@
// ========================================= Configurable Knobs =========================================
// data tid rd wb warp_num read write
`define MRVQ_METADATA_SIZE (32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
`define MRVQ_METADATA_SIZE (32 + $clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(`NUMBER_REQUESTS))
`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(`NUMBER_REQUESTS))
`define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
`define vx_clog2(value) $clog2(value)
// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
`define vx_clog2(value) (value == 0 ) ? 0 : \
(value == 1 ) ? 1 : \
`vx_clog2_h(value, 2 ) : \
`vx_clog2_h(value, 3 ) : \
`vx_clog2_h(value, 4 ) : \
`vx_clog2_h(value, 5 ) : \
`vx_clog2_h(value, 6 ) : \
`vx_clog2_h(value, 7 ) : \
`vx_clog2_h(value, 8 ) : \
`vx_clog2_h(value, 9 ) : \
`vx_clog2_h(value, 10) : \
`vx_clog2_h(value, 11) : \
`vx_clog2_h(value, 12) : \
`vx_clog2_h(value, 13) : \
`vx_clog2_h(value, 14) : \
`vx_clog2_h(value, 15) : \
`vx_clog2_h(value, 16) : \
`vx_clog2_h(value, 17) : \
`vx_clog2_h(value, 18) : \
`vx_clog2_h(value, 19) : \
`vx_clog2_h(value, 20) : \
`vx_clog2_h(value, 21) : \
`vx_clog2_h(value, 22) : \
`vx_clog2_h(value, 23) : \
`vx_clog2_h(value, 24) : \
`vx_clog2_h(value, 25) : \
`vx_clog2_h(value, 26) : \
`vx_clog2_h(value, 27) : \
`vx_clog2_h(value, 28) : \
`vx_clog2_h(value, 29) : \
`vx_clog2_h(value, 30) : \
`vx_clog2_h(value, 31) : \
0
// `define vx_clog2(value) (value == 0 ) ? 0 : \
// (value == 1 ) ? 1 : \
// `vx_clog2_h(value, 2 ) : \
// `vx_clog2_h(value, 3 ) : \
// `vx_clog2_h(value, 4 ) : \
// `vx_clog2_h(value, 5 ) : \
// `vx_clog2_h(value, 6 ) : \
// `vx_clog2_h(value, 7 ) : \
// `vx_clog2_h(value, 8 ) : \
// `vx_clog2_h(value, 9 ) : \
// `vx_clog2_h(value, 10) : \
// `vx_clog2_h(value, 11) : \
// `vx_clog2_h(value, 12) : \
// `vx_clog2_h(value, 13) : \
// `vx_clog2_h(value, 14) : \
// `vx_clog2_h(value, 15) : \
// `vx_clog2_h(value, 16) : \
// `vx_clog2_h(value, 17) : \
// `vx_clog2_h(value, 18) : \
// `vx_clog2_h(value, 19) : \
// `vx_clog2_h(value, 20) : \
// `vx_clog2_h(value, 21) : \
// `vx_clog2_h(value, 22) : \
// `vx_clog2_h(value, 23) : \
// `vx_clog2_h(value, 24) : \
// `vx_clog2_h(value, 25) : \
// `vx_clog2_h(value, 26) : \
// `vx_clog2_h(value, 27) : \
// `vx_clog2_h(value, 28) : \
// `vx_clog2_h(value, 29) : \
// `vx_clog2_h(value, 30) : \
// `vx_clog2_h(value, 31) : \
// 0
`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS
@@ -91,40 +94,43 @@
`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
// Offset is fixed
`define OFFSET_ADDR_NUM_BITS 2
`define OFFSET_SIZE_END 1
`define OFFSET_ADDR_START 0
`define OFFSET_ADDR_END 1
`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
`define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS)
`define WORD_SELECT_NUM_BITS $clog2(`BANK_LINE_SIZE_WORDS)
`define WORD_SELECT_SIZE_END `WORD_SELECT_NUM_BITS
`define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END
`define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:WORD_SELECT_SIZE_END
`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:`WORD_SELECT_SIZE_END
`define BANK_SELECT_NUM_BITS `vx_clog2(`NUMBER_BANKS)
`define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS)
`define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS
`define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END
`define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START
`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0
`define LINE_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_COUNT)
`define LINE_SELECT_NUM_BITS $clog2(`BANK_LINE_COUNT)
`define LINE_SELECT_SIZE_END `LINE_SELECT_NUM_BITS
`define LINE_SELECT_ADDR_START 1+`BANK_SELECT_ADDR_END
`define LINE_SELECT_ADDR_END `LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START
`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0
`define TAG_SELECT_NUM_BITS 32-`LINE_SELECT_ADDR_RNG+1
`define TAG_SELECT_NUM_BITS 32-(`OFFSET_ADDR_NUM_BITS + `WORD_SELECT_NUM_BITS + `BANK_SELECT_NUM_BITS + `LINE_SELECT_NUM_BITS)
`define TAG_SELECT_SIZE_END `TAG_SELECT_NUM_BITS
`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_RNG
`define TAG_SELECT_ADDR_END `TAG_SELECT_SIZE_END+`TAG_SELECT_ADDR_START
`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START
`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_END
`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START
`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0
`define BASE_ADDR_MASK (~((1<<`WORD_SELECT_ADDR_END)-1))
`endif

6
rtl/VX_cache/VX_cache_core_req_bank_sel.v
View File

@@ -7,16 +7,18 @@ module VX_cache_core_req_bank_sel (
output reg [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids
);
wire[31:0] req_address;
generate
integer curr_req;
always @(*) begin
per_bank_valids = 0;
for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin
if (`NUMBER_BANKS == 1) begin
// If there is only one bank, then only map requests to that bank
per_bank_valids[0][curr_req] <= core_req_valid[curr_req];
assign per_bank_valids[0][curr_req] = core_req_valid[curr_req];
end else begin
per_bank_valids[core_req_addr[`BANK_SELECT_ADDR_RNG]][curr_req] <= core_req_valid[curr_req];
assign per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
end
end
end

4
rtl/VX_cache/VX_cache_dfq_queue.v
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@@ -33,7 +33,7 @@ module VX_cache_dfq_queue
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty;
VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`dFQQ_SIZE)) dfqq_queue(
VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
@@ -62,7 +62,7 @@ module VX_cache_dfq_queue
assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index));
always @(posedge clk or reset) begin
always @(posedge clk) begin
if (reset) begin
use_per_bank_dram_fill_req <= 0;
use_per_bank_dram_fill_req_addr <= 0;

16
rtl/VX_cache/VX_cache_dram_req_arb.v
View File

@@ -12,10 +12,10 @@ module VX_cache_dram_req_arb (
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
// DFQ Request
output wire[`NUMBER_BANKS-1] per_bank_dram_wb_queue_pop,
input wire[`NUMBER_BANKS-1] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
// real Dram request
output wire dram_req,
@@ -29,10 +29,10 @@ module VX_cache_dram_req_arb (
wire dfqq_req;
wire dfqq_req_addr;
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_wb_queue_pop);
wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue(
.clk (clk),
.reset (reset),
@@ -48,7 +48,7 @@ module VX_cache_dram_req_arb (
wire dwb_valid;
wire[`vx_log2(`NUMBER_BANKS)-1:0] dwb_bank;
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
.valids(per_bank_dram_wb_req),
.index (dwb_bank),
@@ -62,7 +62,7 @@ module VX_cache_dram_req_arb (
assign dram_req = dwb_valid || dfqq_req;
assign dram_req_write = dwb_valid;
assign dram_req_read = dfqq_req && !dwb_valid;
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = `BANK_LINE_SIZE_BYTES;
assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;

4
rtl/VX_cache/VX_cache_miss_resrv.v
View File

@@ -69,7 +69,7 @@ module VX_cache_miss_resrv (
wire update_ready = (|make_ready);
integer i;
always @(posedge clk or reset) begin
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0;
valid_table <= 0;
@@ -85,7 +85,7 @@ module VX_cache_miss_resrv (
end
if (update_ready) begin
ready_table = ready_table | make_ready;
ready_table <= ready_table | make_ready;
end
if (miss_resrv_pop && dequeue_possible) begin

12
rtl/VX_cache/VX_cache_req_queue.v
View File

@@ -69,11 +69,11 @@ module VX_cache_req_queue (
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
VX_generic_queue #(.DATAW(`NUMBER_REQUESTS * (1+32+32+5+2+(`NW_M1+1)+3+3)), .SIZE(`REQQ_SIZE)) reqq_queue(
VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({bank_valids, bank_addr, bank_writedata, bank_rd, bank_wb, bank_warp_num, bank_mem_read, bank_mem_write}),
.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}),
.pop (pop_qual),
.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}),
.empty (reqq_empty),
@@ -82,7 +82,7 @@ module VX_cache_req_queue (
assign qual_valids = use_empty ? out_per_valids : use_per_valids;
assign qual_valids = use_empty ? out_per_valids : out_empty ? 0 : use_per_valids;
assign qual_addr = use_empty ? out_per_addr : use_per_addr;
assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata;
assign qual_rd = use_empty ? out_per_rd : use_per_rd;
@@ -105,13 +105,13 @@ module VX_cache_req_queue (
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
assign reqq_req_rd_st0 = qual_rd;
assign reqq_req_wb_st0 = qual_wb;
assign reqq_req_warp_num_st0 = qual_warp_num
assign reqq_req_warp_num_st0 = qual_warp_num;
assign reqq_req_mem_read_st0 = qual_mem_read;
assign reqq_req_mem_write_st0 = qual_mem_write;
assign updated_valids = qual_valids & (~(1 << qual_request_index));
always @(posedge clk or reset) begin
always @(posedge clk) begin
if (reset) begin
use_per_valids <= 0;
use_per_addr <= 0;
@@ -131,6 +131,8 @@ module VX_cache_req_queue (
use_per_warp_num <= qual_warp_num;
use_per_mem_read <= qual_mem_read;
use_per_mem_write <= qual_mem_write;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= updated_valids;
end
end
end

29
rtl/VX_cache/VX_cache_wb_sel_merge.v
View File

@@ -4,6 +4,7 @@
module VX_cache_wb_sel_merge (
// Per Bank WB
input wire [`NUMBER_BANKS-1:0] per_bank_wb_valid,
input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
@@ -15,19 +16,19 @@ module VX_cache_wb_sel_merge (
// Core Writeback
input wire core_no_wb_slot,
output reg [`NUMBER_REQUESTS-1:0] core_wb_valid,
output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata
output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output wire [`NW_M1:0] core_wb_warp_num
);
wire [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual;
reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual;
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{core_no_wb_slot}};
wire[`NUMBER_BANKS-1:0] bank_wants_wb;
genvar curr_bank;
generate
integer curr_bank;
for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
end
@@ -47,17 +48,17 @@ module VX_cache_wb_sel_merge (
assign core_wb_req_wb = per_bank_wb_wb [main_bank_index];
assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
genvar this_bank;
generate
integer this_bank;
for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin
if ((per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])
&& (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])) begin
assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
assign per_bank_wb_pop_unqual[this_bank] = 1;
end else
assign per_bank_wb_pop_unqual[this_bank] = 0;
always @(*) begin
for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin
if (found_bank && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
assign per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
assign per_bank_wb_pop_unqual[this_bank] = 0;
end
end
end
endgenerate

24
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -54,7 +54,7 @@ module VX_tag_data_access (
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1)
.read_data (qual_read_data_st1),
.write_enable(use_write_enable),
.write_fill (writefill_st1e),
@@ -62,7 +62,7 @@ module VX_tag_data_access (
.write_data (use_write_data)
);
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_c0 (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
@@ -74,12 +74,12 @@ module VX_tag_data_access (
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_cc (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]})
.in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}),
.out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] })
);
end
@@ -120,14 +120,14 @@ module VX_tag_data_access (
wire[31:0] lw_data = (data_unQual);
wire[31:0] sw_data = writedata_st1e;
wire[31:0] sw_data = writeword_st1e;
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writedata_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writedata_st1e[7:0], {24{1'b0}}} :
writedata_st1e;
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e;
wire[31:0] sh_data = b2 ? {writedata_st1e[15:0], {16{1'b0}}} : writedata_st1e;
wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e;
@@ -158,7 +158,7 @@ module VX_tag_data_access (
wire[`BANK_LINE_SIZE_RNG][31:0] data_write;
genvar g;
generate
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
for (g = 0; g < `BANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g) && should_write;
assign we[g] = (force_write) ? 4'b1111 :
@@ -177,7 +177,7 @@ module VX_tag_data_access (
///////////////////////
assign readword_st1e = data_Qual;
assign miss_st1e = valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)
assign miss_st1e = (valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e));
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;

19
rtl/VX_cache/VX_tag_data_structure.v
View File

@@ -15,19 +15,20 @@ module VX_tag_data_structure (
);
reg[`BANK_LINE_SIZE_RNG:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`BANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0];
reg valid[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
assign read_valid <= valid[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_dirty <= dirty[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_tag <= tag [read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_data <= data [read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_tag = tag [read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_data = data [read_addr[`LINE_SELECT_ADDR_RNG]];
wire going_to_write = (|write_enable);
integer f;
always @(posedge clk) begin
if (going_to_write) begin
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
@@ -40,10 +41,10 @@ module VX_tag_data_structure (
end
for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin
if (write_enable[f][0]) data[addr[`LINE_SELECT_ADDR_RNG]][f][0] <= data_write[f][7 :0 ];
if (write_enable[f][1]) data[addr[`LINE_SELECT_ADDR_RNG]][f][1] <= data_write[f][15:8 ];
if (write_enable[f][2]) data[addr[`LINE_SELECT_ADDR_RNG]][f][2] <= data_write[f][23:16];
if (write_enable[f][3]) data[addr[`LINE_SELECT_ADDR_RNG]][f][3] <= data_write[f][31:24];
if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ];
if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ];
if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16];
if (write_enable[f][3]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][3] <= write_data[f][31:24];
end
end

7
rtl/VX_define.v
View File

@@ -1,6 +1,9 @@
`include "./VX_define_synth.v"
// `include "./VX_cache/VX_cache_config.v"
// `ifndef VX_DEFINE
// `define VX_DEFINE
`define NT_M1 (`NT-1)
@@ -267,3 +270,7 @@
`define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +`SHARED_MEMORY_LOG_WORDS_PER_READ-1)
`define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1)
`define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1)
// `endif

9
rtl/VX_define_synth.v
View File

@@ -1,2 +1,9 @@
`define NT 4
// `ifndef VX_DEFINE_SYNTH
// `define VX_DEFINE_SYNTH
`define NT 2
`define NW 8
// `endif

6
rtl/VX_dmem_controller.v
View File

@@ -66,8 +66,8 @@ module VX_dmem_controller (
.clk (clk),
.reset (reset),
.in_valid (sm_driver_in_valid),
.in_address(cache_driver_in_address),
.in_data (cache_driver_in_data),
.in_address(VX_dcache_req.core_req_addr),
.in_data (VX_dcache_req.core_req_writedata),
.mem_read (sm_driver_in_mem_read),
.mem_write (sm_driver_in_mem_write),
.out_valid (cache_driver_out_valid),
@@ -117,7 +117,7 @@ module VX_dmem_controller (
.dram_req_read (VX_gpu_dcache_dram_req.dram_req_read),
.dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr),
.dram_req_size (VX_gpu_dcache_dram_req.dram_req_size),
.dram_req_data (VX_gpu_dcache_dram_req.dram_req_data),
.dram_req_data (VX_gpu_dcache_dram_req.dram_req_data)
);

6
rtl/VX_fetch.v
View File

@@ -98,9 +98,9 @@ module VX_fetch (
.scheduled_warp (scheduled_warp)
);
assign fe_inst_meta_fi.warp_num = warp_num;
assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}};
assign fe_inst_meta_fi.warp_num = warp_num;
assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}};
assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc;

6
rtl/VX_front_end.v
View File

@@ -58,6 +58,10 @@ VX_fetch vx_fetch(
);
wire freeze_fi_reg = total_freeze || icache_stage_delay;
VX_f_d_reg vx_f_i_reg(
.clk (clk),
.reset (reset),
@@ -77,7 +81,7 @@ VX_icache_stage VX_icache_stage(
);
VX_f_d_reg vx_i_d_reg(
VX_i_d_reg vx_i_d_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),

14
rtl/VX_generic_queue.v
View File

@@ -3,7 +3,7 @@
module VX_generic_queue
#(
parameter DATAW = 4,
parameter SIZE = 16
parameter SIZE = 277
)
(
input wire clk,
@@ -18,7 +18,7 @@ module VX_generic_queue
);
reg[SIZE-1:0] data[DATAW-1:0];
reg[DATAW-1:0] data[SIZE-1:0];
reg[$clog2(SIZE)-1:0] head;
reg[$clog2(SIZE)-1:0] tail;
@@ -26,19 +26,21 @@ module VX_generic_queue
assign full = head == (tail+1);
integer i;
always @(posedge clk or reset) begin
always @(posedge clk) begin
if (reset) begin
head <= 0;
tail <= 0;
for (i = 0; i < SIZE; i=i+1) data[i] <= DATAW'0;
for (i = 0; i < SIZE; i=i+1) begin
data[i] <= {DATAW{1'0}};
end
end else begin
if (push && !full) begin
data[tail] <= in_data;
tail = tail+1;
tail <= tail+1;
end
if (pop) begin
head = head + 1;
head <= head + 1;
end
end

19
rtl/VX_generic_register.v
View File

@@ -1,20 +1,17 @@
module VX_generic_register
#(
parameter N = 1
)
#( parameter N = 1)
(
input clk,
input reset,
input stall,
input flush,
input[N-1:0] in,
output [N-1:0] out
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[(N-1):0] in,
output wire[(N-1):0] out
);
reg[N-1:0] value;
reg[(N-1):0] value;

11
rtl/Vortex.v
View File

@@ -1,6 +1,6 @@
`include "VX_define.v"
// `include "VX_define.v"
`include "./VX_cache/VX_cache_config.v"
module Vortex
/*#(
@@ -51,15 +51,13 @@ module Vortex
reg[31:0] icache_banks = `ICACHE_BANKS;
reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK;
reg[31:0] number_threads = `NT;
reg[31:0] number_warps = `NW;
always @(posedge clk) begin
icache_banks <= icache_banks;
icache_num_words_per_block <= icache_num_words_per_block;
dcache_banks <= dcache_banks;
dcache_num_words_per_block <= dcache_num_words_per_block;
number_threads <= number_threads;
number_warps <= number_warps;
end
@@ -133,7 +131,6 @@ for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin
assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////

4
rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -13,9 +13,7 @@ module VX_f_d_reg (
wire flush = 1'b0;
wire stall = in_freeze == 1'b1;
VX_generic_register #(.N(64 + `NW_M1 + 1 + `NT)) f_d_reg
(
VX_generic_register #( .N(64+`NW_M1+1+`NT) ) f_d_reg (
.clk (clk),
.reset(reset),
.stall(stall),

27
rtl/pipe_regs/VX_i_d_reg.v Normal file
View File

@@ -0,0 +1,27 @@
`include "../VX_define.v"
module VX_i_d_reg (
input wire clk,
input wire reset,
input wire in_freeze,
VX_inst_meta_inter fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de
);
wire flush = 1'b0;
wire stall = in_freeze == 1'b1;
VX_generic_register #( .N( 64 + `NW_M1 + 1 + `NT ) ) i_d_reg (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
);
endmodule