fixed SCOPE interface
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@@ -6,7 +6,7 @@ module VX_pipeline #(
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`SCOPE_SIGNALS_ISTAGE_IO
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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// Clock
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input wire clk,
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@@ -126,6 +126,7 @@ module VX_pipeline #(
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VX_fetch #(
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.CORE_ID(CORE_ID)
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) fetch (
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`SCOPE_SIGNALS_ISTAGE_BIND
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.clk (clk),
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.reset (reset),
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.icache_req_if (core_icache_req_if),
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@@ -171,6 +172,7 @@ module VX_pipeline #(
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.CORE_ID(CORE_ID)
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) execute (
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_EX_BIND
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.clk (clk),
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.reset (reset),
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@@ -245,10 +247,6 @@ module VX_pipeline #(
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assign core_icache_rsp_if.tag = icache_rsp_tag;
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assign icache_rsp_ready = core_icache_rsp_if.ready;
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`SCOPE_ASSIGN (scope_busy, busy);
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`SCOPE_ASSIGN (scope_schedule_delay, schedule_delay);
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`SCOPE_ASSIGN (scope_mem_delay, mem_delay);
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`SCOPE_ASSIGN (scope_exec_delay, exec_delay);
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`SCOPE_ASSIGN (scope_gpr_stage_delay, gpr_delay);
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`SCOPE_ASSIGN (scope_busy, busy);
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endmodule
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