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accelerator cisc

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This commit is contained in:
Richard Yan
2024-05-07 13:58:32 -07:00
parent 14d1552f08
commit c9a3eaad79
7 changed files with 66 additions and 12 deletions
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12
hw/rtl/VX_core_wrapper.sv
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@@ -125,6 +125,12 @@ module Vortex import VX_gpu_pkg::*; #(
// output fpu_killm,
// output fpu_keep_clock_enabled,
// accelerator cisc csr --------------------------------
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en,
output finished,
input traceStall,
@@ -414,7 +420,11 @@ module Vortex import VX_gpu_pkg::*; #(
.sim_ebreak (sim_ebreak),
.sim_wb_value (sim_wb_value),
.busy (busy)
.busy (busy),
.acc_read_in (acc_read_in),
.acc_write_out (acc_write_out),
.acc_write_en (acc_write_en)
);
// VX_dcache_req_if #(

3
hw/rtl/VX_types.vh
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@@ -184,4 +184,7 @@
`define VX_CSR_NUM_WARPS 12'hFC1
`define VX_CSR_NUM_CORES 12'hFC2
// CISC Accelerator Invocation
`define VX_CSR_ACCEL_CISC 12'hACC
`endif // VX_TYPES_VH

12
hw/rtl/core/VX_core.sv
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@@ -47,7 +47,11 @@ module VX_core import VX_gpu_pkg::*; #(
output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
// Status
output wire busy //stays 1 when busy, 0 when done (termination) detect the negative edge
output wire busy, //stays 1 when busy, 0 when done (termination) detect the negative edge
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en
);
VX_schedule_if schedule_if();
VX_fetch_if fetch_if();
@@ -214,7 +218,11 @@ module VX_core import VX_gpu_pkg::*; #(
.lsu_commit_if (lsu_commit_if),
.sfu_commit_if (sfu_commit_if),
.sim_ebreak (sim_ebreak)
.sim_ebreak (sim_ebreak),
.acc_read_in (acc_read_in),
.acc_write_out (acc_write_out),
.acc_write_en (acc_write_en)
);
VX_commit #(

13
hw/rtl/core/VX_csr_data.sv
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@@ -58,7 +58,11 @@ import VX_fpu_pkg::*;
input wire [`UUID_WIDTH-1:0] write_uuid,
input wire [`NW_WIDTH-1:0] write_wid,
input wire [`VX_CSR_ADDR_BITS-1:0] write_addr,
input wire [31:0] write_data
input wire [31:0] write_data,
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en
);
`UNUSED_VAR (reset)
@@ -108,6 +112,9 @@ import VX_fpu_pkg::*;
end
`endif
assign acc_write_en = write_enable && (write_addr == `VX_CSR_ACCEL_CISC);
assign acc_write_out = write_data;
always @(posedge clk) begin
if (write_enable) begin
case (write_addr)
@@ -116,6 +123,7 @@ import VX_fpu_pkg::*;
`VX_CSR_FRM,
`VX_CSR_FCSR,
`endif
`VX_CSR_ACCEL_CISC,
`VX_CSR_SATP,
`VX_CSR_MSTATUS,
`VX_CSR_MNSTATUS,
@@ -143,7 +151,7 @@ import VX_fpu_pkg::*;
read_data_ro_r = '0;
read_data_rw_r = '0;
read_addr_valid_r = 1;
case (read_addr)
case (read_addr)
`VX_CSR_MVENDORID : read_data_ro_r = 32'(`VENDOR_ID);
`VX_CSR_MARCHID : read_data_ro_r = 32'(`ARCHITECTURE_ID);
`VX_CSR_MIMPID : read_data_ro_r = 32'(`IMPLEMENTATION_ID);
@@ -179,6 +187,7 @@ import VX_fpu_pkg::*;
`VX_CSR_MEPC,
`VX_CSR_PMPCFG0,
`VX_CSR_PMPADDR0 : read_data_ro_r = 32'(0);
`VX_CSR_ACCEL_CISC : read_data_ro_r = 32'(acc_read_in);
default: begin
read_addr_valid_r = 0;

12
hw/rtl/core/VX_csr_unit.sv
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@@ -34,7 +34,11 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
VX_commit_csr_if.slave commit_csr_if,
VX_sched_csr_if.slave sched_csr_if,
VX_execute_if.slave execute_if,
VX_commit_if.master commit_if
VX_commit_if.master commit_if,
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en
);
`UNUSED_PARAM (CORE_ID)
localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
@@ -102,7 +106,11 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
.write_uuid (execute_if.data.uuid),
.write_wid (execute_if.data.wid),
.write_addr (csr_addr),
.write_data (csr_write_data)
.write_data (csr_write_data),
.acc_read_in (acc_read_in),
.acc_write_out (acc_write_out),
.acc_write_en (acc_write_en)
);
// CSR read

12
hw/rtl/core/VX_execute.sv
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@@ -54,7 +54,11 @@ module VX_execute import VX_gpu_pkg::*; #(
VX_warp_ctl_if.master warp_ctl_if,
// simulation helper signals
output wire sim_ebreak
output wire sim_ebreak,
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en
);
`ifdef EXT_F_ENABLE
@@ -124,7 +128,11 @@ module VX_execute import VX_gpu_pkg::*; #(
.commit_csr_if (commit_csr_if),
.sched_csr_if (sched_csr_if),
.warp_ctl_if (warp_ctl_if),
.commit_if (sfu_commit_if)
.commit_if (sfu_commit_if),
.acc_read_in (acc_read_in),
.acc_write_out (acc_write_out),
.acc_write_en (acc_write_en)
);
// simulation helper signal to get RISC-V tests Pass/Fail status

14
hw/rtl/core/VX_sfu_unit.sv
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@@ -37,7 +37,11 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
VX_commit_if.master commit_if [`ISSUE_WIDTH],
VX_commit_csr_if.slave commit_csr_if,
VX_sched_csr_if.slave sched_csr_if,
VX_warp_ctl_if.master warp_ctl_if
VX_warp_ctl_if.master warp_ctl_if,
input wire [31:0] acc_read_in,
output wire [31:0] acc_write_out,
output wire acc_write_en
);
`UNUSED_PARAM (CORE_ID)
localparam BLOCK_SIZE = 1;
@@ -134,8 +138,12 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
.sched_csr_if (sched_csr_if),
.commit_csr_if (commit_csr_if),
.commit_if (csr_commit_if)
);
.commit_if (csr_commit_if),
.acc_read_in (acc_read_in),
.acc_write_out (acc_write_out),
.acc_write_en (acc_write_en)
);
assign rsp_arb_valid_in[RSP_ARB_IDX_CSRS] = csr_commit_if.valid;
assign rsp_arb_data_in[RSP_ARB_IDX_CSRS] = csr_commit_if.data;