cache bindings and memory perf refactory
This commit is contained in:
Blaise Tine
@@ -178,7 +178,26 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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uint64_t instrs = 0;
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uint64_t cycles = 0;
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#ifdef PERF_ENABLE
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#ifdef PERF_ENABLE
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auto calcRatio = [&](uint64_t part, uint64_t total)->int {
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if (total == 0)
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return 0;
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return int((1.0 - (double(part) / double(total))) * 100);
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};
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auto caclAvgLatency = [&](uint64_t sum, uint64_t requests)->int {
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if (requests == 0)
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return 0;
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return int(double(sum) / double(requests));
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};
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auto calcUtilization = [&](uint64_t count, uint64_t stalls)->int {
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if (count == 0)
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return 0;
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return int((double(count) / double(count + stalls)) * 100);
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};
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auto perf_class = gAutoPerfDump.get_perf_class();
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// PERF: pipeline stalls
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@@ -192,21 +211,7 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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uint64_t loads = 0;
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uint64_t stores = 0;
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uint64_t ifetch_lat = 0;
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uint64_t load_lat = 0;
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// PERF: Icache
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uint64_t icache_reads = 0;
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uint64_t icache_read_misses = 0;
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// PERF: Dcache
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uint64_t dcache_reads = 0;
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uint64_t dcache_writes = 0;
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uint64_t dcache_read_misses = 0;
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uint64_t dcache_write_misses = 0;
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uint64_t dcache_bank_stalls = 0;
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uint64_t dcache_mshr_stalls = 0;
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// PERF: shared memory
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uint64_t smem_reads = 0;
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uint64_t smem_writes = 0;
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uint64_t smem_bank_stalls = 0;
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uint64_t load_lat = 0;
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// PERF: l2cache
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uint64_t l2cache_reads = 0;
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uint64_t l2cache_writes = 0;
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@@ -232,6 +237,19 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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if (ret != 0)
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return ret;
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#ifdef PERF_ENABLE
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uint64_t isa_flags;
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ret = vx_dev_caps(hdevice, VX_CAPS_ISA_FLAGS, &isa_flags);
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if (ret != 0)
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return ret;
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bool icache_enable = isa_flags & VX_ISA_EXT_ICACHE;
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bool dcache_enable = isa_flags & VX_ISA_EXT_DCACHE;
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bool l2cache_enable = isa_flags & VX_ISA_EXT_L2CACHE;
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bool l3cache_enable = isa_flags & VX_ISA_EXT_L3CACHE;
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bool smem_enable = isa_flags & VX_ISA_EXT_SMEM;
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#endif
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std::vector<uint8_t> staging_buf(64* sizeof(uint32_t));
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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@@ -240,13 +258,6 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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if (ret != 0)
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return ret;
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uint64_t instrs_per_core = get_csr_64(staging_buf.data(), VX_CSR_MINSTRET);
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uint64_t cycles_per_core = get_csr_64(staging_buf.data(), VX_CSR_MCYCLE);
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float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
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instrs += instrs_per_core;
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cycles = std::max<uint64_t>(cycles_per_core, cycles);
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#ifdef PERF_ENABLE
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switch (perf_class) {
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case VX_DCR_MPM_CLASS_CORE: {
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@@ -291,52 +302,78 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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// ifetch latency
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uint64_t ifetch_lat_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_IFETCH_LAT);
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if (num_cores > 1) {
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int mem_avg_lat = (int)(double(ifetch_lat_per_core) / double(ifetches_per_core));
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int mem_avg_lat = caclAvgLatency(ifetch_lat_per_core, ifetches_per_core);
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fprintf(stream, "PERF: core%d: ifetch latency=%d cycles\n", core_id, mem_avg_lat);
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}
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ifetch_lat += ifetch_lat_per_core;
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// load latency
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uint64_t load_lat_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_LOAD_LAT);
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if (num_cores > 1) {
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int mem_avg_lat = (int)(double(load_lat_per_core) / double(loads_per_core));
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int mem_avg_lat = caclAvgLatency(load_lat_per_core, loads_per_core);
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fprintf(stream, "PERF: core%d: load latency=%d cycles\n", core_id, mem_avg_lat);
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}
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load_lat += load_lat_per_core;
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} break;
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case VX_DCR_MPM_CLASS_MEM: {
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if (0 == core_id) {
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// PERF: Icache
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icache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_READS);
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icache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_MISS_R);
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// PERF: Dcache
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dcache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_READS);
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dcache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_WRITES);
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dcache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_R);
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dcache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_W);
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dcache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_BANK_ST);
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dcache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MSHR_ST);
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if (smem_enable) {
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// PERF: smem
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smem_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_READS);
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smem_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_WRITES);
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smem_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_BANK_ST);
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uint64_t smem_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_READS);
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uint64_t smem_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_WRITES);
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uint64_t smem_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_BANK_ST);
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int smem_bank_utilization = calcUtilization(smem_reads + smem_writes, smem_bank_stalls);
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fprintf(stream, "PERF: core%d: smem reads=%ld\n", core_id, smem_reads);
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fprintf(stream, "PERF: core%d: smem writes=%ld\n", core_id, smem_writes);
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fprintf(stream, "PERF: core%d: smem bank stalls=%ld (utilization=%d%%)\n", core_id, smem_bank_stalls, smem_bank_utilization);
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}
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if (icache_enable) {
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// PERF: Icache
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uint64_t icache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_READS);
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uint64_t icache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_MISS_R);
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int icache_read_hit_ratio = calcRatio(icache_read_misses, icache_reads);
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fprintf(stream, "PERF: core%d: icache reads=%ld\n", core_id, icache_reads);
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fprintf(stream, "PERF: core%d: icache read misses=%ld (hit ratio=%d%%)\n", core_id, icache_read_misses, icache_read_hit_ratio);
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}
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if (dcache_enable) {
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// PERF: Dcache
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uint64_t dcache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_READS);
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uint64_t dcache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_WRITES);
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uint64_t dcache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_R);
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uint64_t dcache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_W);
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uint64_t dcache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_BANK_ST);
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uint64_t dcache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MSHR_ST);
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int dcache_read_hit_ratio = calcRatio(dcache_read_misses, dcache_reads);
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int dcache_write_hit_ratio = calcRatio(dcache_write_misses, dcache_writes);
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int dcache_bank_utilization = calcUtilization(dcache_reads + dcache_writes, dcache_bank_stalls);
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fprintf(stream, "PERF: core%d: dcache reads=%ld\n", core_id, dcache_reads);
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fprintf(stream, "PERF: core%d: dcache writes=%ld\n", core_id, dcache_writes);
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fprintf(stream, "PERF: core%d: dcache read misses=%ld (hit ratio=%d%%)\n", core_id, dcache_read_misses, dcache_read_hit_ratio);
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fprintf(stream, "PERF: core%d: dcache write misses=%ld (hit ratio=%d%%)\n", core_id, dcache_write_misses, dcache_write_hit_ratio);
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fprintf(stream, "PERF: core%d: dcache bank stalls=%ld (utilization=%d%%)\n", core_id, dcache_bank_stalls, dcache_bank_utilization);
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fprintf(stream, "PERF: core%d: dcache mshr stalls=%ld\n", core_id, dcache_mshr_stalls);
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}
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if (l2cache_enable) {
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// PERF: L2cache
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l2cache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_READS);
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l2cache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_WRITES);
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l2cache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_R);
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l2cache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_W);
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l2cache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_BANK_ST);
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l2cache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MSHR_ST);
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// PERF: L3cache
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l3cache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_READS);
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l3cache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_WRITES);
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l3cache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_R);
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l3cache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_W);
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l3cache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_BANK_ST);
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l3cache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MSHR_ST);
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l2cache_reads += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_READS);
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l2cache_writes += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_WRITES);
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l2cache_read_misses += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_R);
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l2cache_write_misses += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_W);
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l2cache_bank_stalls += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_BANK_ST);
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l2cache_mshr_stalls += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MSHR_ST);
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}
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if (0 == core_id) {
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if (l3cache_enable) {
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// PERF: L3cache
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l3cache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_READS);
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l3cache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_WRITES);
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l3cache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_R);
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l3cache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_W);
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l3cache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_BANK_ST);
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l3cache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MSHR_ST);
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}
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// PERF: memory
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mem_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_MEM_READS);
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@@ -347,11 +384,15 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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default:
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break;
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}
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#endif
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}
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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#endif
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uint64_t instrs_per_core = get_csr_64(staging_buf.data(), VX_CSR_MINSTRET);
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uint64_t cycles_per_core = get_csr_64(staging_buf.data(), VX_CSR_MCYCLE);
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float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
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instrs += instrs_per_core;
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cycles = std::max<uint64_t>(cycles_per_core, cycles);
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}
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#ifdef PERF_ENABLE
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switch (perf_class) {
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@@ -368,52 +409,51 @@ extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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fprintf(stream, "PERF: loads=%ld\n", loads);
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fprintf(stream, "PERF: stores=%ld\n", stores);
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fprintf(stream, "PERF: ifetch latency=%d cycles\n", ifetch_avg_lat);
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fprintf(stream, "PERF: load latency=%d cycles\n", load_avg_lat);
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fprintf(stream, "PERF: load latency=%d cycles\n", load_avg_lat);
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} break;
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case VX_DCR_MPM_CLASS_MEM: {
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int icache_read_hit_ratio = (int)((1.0 - (double(icache_read_misses) / double(icache_reads))) * 100);
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int dcache_read_hit_ratio = (int)((1.0 - (double(dcache_read_misses) / double(dcache_reads))) * 100);
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int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_write_misses) / double(dcache_writes))) * 100);
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int dcache_bank_utilization = (int)((double(dcache_reads + dcache_writes) / double(dcache_reads + dcache_writes + dcache_bank_stalls)) * 100);
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int l2cache_read_hit_ratio = (int)((1.0 - (double(l2cache_read_misses) / double(l2cache_reads))) * 100);
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int l2cache_write_hit_ratio = (int)((1.0 - (double(l2cache_write_misses) / double(l2cache_writes))) * 100);
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int l2cache_bank_utilization = (int)((double(l2cache_reads + l2cache_writes) / double(l2cache_reads + l2cache_writes + l2cache_bank_stalls)) * 100);
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int l3cache_read_hit_ratio = (int)((1.0 - (double(l3cache_read_misses) / double(l3cache_reads))) * 100);
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int l3cache_write_hit_ratio = (int)((1.0 - (double(l3cache_write_misses) / double(l3cache_writes))) * 100);
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int l3cache_bank_utilization = (int)((double(l3cache_reads + l3cache_writes) / double(l3cache_reads + l3cache_writes + l3cache_bank_stalls)) * 100);
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int smem_bank_utilization = (int)((double(smem_reads + smem_writes) / double(smem_reads + smem_writes + smem_bank_stalls)) * 100);
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int mem_avg_lat = (int)(double(mem_lat) / double(mem_reads));
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fprintf(stream, "PERF: icache reads=%ld\n", icache_reads);
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fprintf(stream, "PERF: icache read misses=%ld (hit ratio=%d%%)\n", icache_read_misses, icache_read_hit_ratio);
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fprintf(stream, "PERF: dcache reads=%ld\n", dcache_reads);
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fprintf(stream, "PERF: dcache writes=%ld\n", dcache_writes);
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fprintf(stream, "PERF: dcache read misses=%ld (hit ratio=%d%%)\n", dcache_read_misses, dcache_read_hit_ratio);
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fprintf(stream, "PERF: dcache write misses=%ld (hit ratio=%d%%)\n", dcache_write_misses, dcache_write_hit_ratio);
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fprintf(stream, "PERF: dcache bank stalls=%ld (utilization=%d%%)\n", dcache_bank_stalls, dcache_bank_utilization);
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fprintf(stream, "PERF: dcache mshr stalls=%ld\n", dcache_mshr_stalls);
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fprintf(stream, "PERF: smem reads=%ld\n", smem_reads);
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fprintf(stream, "PERF: smem writes=%ld\n", smem_writes);
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fprintf(stream, "PERF: smem bank stalls=%ld (utilization=%d%%)\n", smem_bank_stalls, smem_bank_utilization);
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fprintf(stream, "PERF: l2cache reads=%ld\n", l2cache_reads);
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fprintf(stream, "PERF: l2cache writes=%ld\n", l2cache_writes);
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fprintf(stream, "PERF: l2cache read misses=%ld (hit ratio=%d%%)\n", l2cache_read_misses, l2cache_read_hit_ratio);
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fprintf(stream, "PERF: l2cache write misses=%ld (hit ratio=%d%%)\n", l2cache_write_misses, l2cache_write_hit_ratio);
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fprintf(stream, "PERF: l2cache bank stalls=%ld (utilization=%d%%)\n", l2cache_bank_stalls, l2cache_bank_utilization);
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fprintf(stream, "PERF: l2cache mshr stalls=%ld\n", l2cache_mshr_stalls);
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fprintf(stream, "PERF: l3cache reads=%ld\n", l3cache_reads);
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fprintf(stream, "PERF: l3cache writes=%ld\n", l3cache_writes);
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fprintf(stream, "PERF: l3cache read misses=%ld (hit ratio=%d%%)\n", l3cache_read_misses, l3cache_read_hit_ratio);
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fprintf(stream, "PERF: l3cache write misses=%ld (hit ratio=%d%%)\n", l3cache_write_misses, l3cache_write_hit_ratio);
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fprintf(stream, "PERF: l3cache bank stalls=%ld (utilization=%d%%)\n", l3cache_bank_stalls, l3cache_bank_utilization);
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fprintf(stream, "PERF: l3cache mshr stalls=%ld\n", l3cache_mshr_stalls);
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case VX_DCR_MPM_CLASS_MEM: {
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if (l2cache_enable) {
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l2cache_reads /= num_cores;
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l2cache_writes /= num_cores;
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l2cache_read_misses /= num_cores;
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l2cache_write_misses /= num_cores;
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l2cache_bank_stalls /= num_cores;
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l2cache_mshr_stalls /= num_cores;
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int l2cache_read_hit_ratio = calcRatio(l2cache_read_misses, l2cache_reads);
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||||
int l2cache_write_hit_ratio = calcRatio(l2cache_write_misses, l2cache_writes);
|
||||
int l2cache_bank_utilization = calcUtilization(l2cache_reads + l2cache_writes, l2cache_bank_stalls);
|
||||
|
||||
fprintf(stream, "PERF: l2cache reads=%ld\n", l2cache_reads);
|
||||
fprintf(stream, "PERF: l2cache writes=%ld\n", l2cache_writes);
|
||||
fprintf(stream, "PERF: l2cache read misses=%ld (hit ratio=%d%%)\n", l2cache_read_misses, l2cache_read_hit_ratio);
|
||||
fprintf(stream, "PERF: l2cache write misses=%ld (hit ratio=%d%%)\n", l2cache_write_misses, l2cache_write_hit_ratio);
|
||||
fprintf(stream, "PERF: l2cache bank stalls=%ld (utilization=%d%%)\n", l2cache_bank_stalls, l2cache_bank_utilization);
|
||||
fprintf(stream, "PERF: l2cache mshr stalls=%ld\n", l2cache_mshr_stalls);
|
||||
}
|
||||
|
||||
if (l3cache_enable) {
|
||||
int l3cache_read_hit_ratio = calcRatio(l3cache_read_misses, l3cache_reads);
|
||||
int l3cache_write_hit_ratio = calcRatio(l3cache_write_misses, l3cache_writes);
|
||||
int l3cache_bank_utilization = calcUtilization(l3cache_reads + l3cache_writes, l3cache_bank_stalls);
|
||||
fprintf(stream, "PERF: l3cache reads=%ld\n", l3cache_reads);
|
||||
fprintf(stream, "PERF: l3cache writes=%ld\n", l3cache_writes);
|
||||
fprintf(stream, "PERF: l3cache read misses=%ld (hit ratio=%d%%)\n", l3cache_read_misses, l3cache_read_hit_ratio);
|
||||
fprintf(stream, "PERF: l3cache write misses=%ld (hit ratio=%d%%)\n", l3cache_write_misses, l3cache_write_hit_ratio);
|
||||
fprintf(stream, "PERF: l3cache bank stalls=%ld (utilization=%d%%)\n", l3cache_bank_stalls, l3cache_bank_utilization);
|
||||
fprintf(stream, "PERF: l3cache mshr stalls=%ld\n", l3cache_mshr_stalls);
|
||||
}
|
||||
|
||||
int mem_avg_lat = caclAvgLatency(mem_lat, mem_reads);
|
||||
fprintf(stream, "PERF: memory requests=%ld (reads=%ld, writes=%ld)\n", (mem_reads + mem_writes), mem_reads, mem_writes);
|
||||
fprintf(stream, "PERF: memory latency=%d cycles\n", mem_avg_lat);
|
||||
} break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
float IPC = (float)(double(instrs) / double(cycles));
|
||||
fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
|
||||
|
||||
fflush(stream);
|
||||
|
||||
|
||||
@@ -47,10 +47,12 @@ typedef void* vx_device_h;
|
||||
#define VX_ISA_STD_Q (1ull << 16)
|
||||
#define VX_ISA_STD_S (1ull << 18)
|
||||
#define VX_ISA_STD_U (1ull << 20)
|
||||
#define VX_ISA_BASE(flags) (1 << (((flags >> 30) & 0x3) + 4))
|
||||
#define VX_ISA_EXT_TEX (1ull << 32)
|
||||
#define VX_ISA_EXT_RASTER (1ull << 33)
|
||||
#define VX_ISA_EXT_ROP (1ull << 34)
|
||||
#define VX_ISA_ARCH(flags) (1 << (((flags >> 30) & 0x3) + 4))
|
||||
#define VX_ISA_EXT_ICACHE (1ull << 32)
|
||||
#define VX_ISA_EXT_DCACHE (1ull << 33)
|
||||
#define VX_ISA_EXT_L2CACHE (1ull << 34)
|
||||
#define VX_ISA_EXT_L3CACHE (1ull << 35)
|
||||
#define VX_ISA_EXT_SMEM (1ull << 36)
|
||||
|
||||
// device memory types
|
||||
#define VX_MEM_TYPE_GLOBAL 0
|
||||
|
||||
Reference in New Issue
Block a user