add tag to tc smem interface

hw/rtl/VX_core_wrapper.sv

@@ -6,7 +6,8 @@ module Vortex import VX_gpu_pkg::*; #(
     parameter CORE_ID = 0,
     parameter TENSOR_FP16 = 0,
     parameter BOOTROM_HANG100 = 32'h10100,
-    parameter NUM_THREADS = 0
+    parameter NUM_THREADS = 0,
+    parameter TC_TAG_WIDTH = 4
 ) (
 
     /* adapt to CoreIO bundle at src/main/scala/tile/Core.scala */
@@ -78,9 +79,11 @@ module Vortex import VX_gpu_pkg::*; #(
     input  [1:0]   tc_a_ready,
     output [1:0]   tc_a_valid,
     output [63:0]  tc_a_bits_address,
-    input  [511:0] tc_d_bits_data,
+    output [2 * TC_TAG_WIDTH - 1:0] tc_a_bits_tag,
     output [1:0]   tc_d_ready,
     input  [1:0]   tc_d_valid,
+    input  [511:0] tc_d_bits_data,
+    input  [2 * TC_TAG_WIDTH - 1:0] tc_d_bits_tag,
 
     // gbar ------------------------------------------------
 
@@ -298,16 +301,19 @@ module Vortex import VX_gpu_pkg::*; #(
     endgenerate
 
     // tc ---------------------------------------------------------------------
-    VX_tc_bus_if tc_p0_bus_if();
+    VX_tc_bus_if #(.TAG_WIDTH(TC_TAG_WIDTH)) tc_p0_bus_if();
-    VX_tc_bus_if tc_p1_bus_if();
+    VX_tc_bus_if #(.TAG_WIDTH(TC_TAG_WIDTH)) tc_p1_bus_if();
     assign tc_a_valid = {tc_p1_bus_if.req_valid, tc_p0_bus_if.req_valid};
-    assign tc_a_bits_address = {tc_p1_bus_if.req_data, tc_p0_bus_if.req_data};
+    assign tc_a_bits_address = {tc_p1_bus_if.req_data.addr, tc_p0_bus_if.req_data.addr};
+    assign tc_a_bits_tag = {tc_p1_bus_if.req_data.tag, tc_p0_bus_if.req_data.tag};
     assign tc_p0_bus_if.req_ready = tc_a_ready[0];
     assign tc_p0_bus_if.rsp_valid = tc_d_valid[0];
-    assign tc_p0_bus_if.rsp_data = tc_d_bits_data[0];
+    assign tc_p0_bus_if.rsp_data.data = tc_d_bits_data[0];
+    assign tc_p0_bus_if.rsp_data.tag = tc_d_bits_tag[0];
     assign tc_p1_bus_if.req_ready = tc_a_ready[1];
     assign tc_p1_bus_if.rsp_valid = tc_d_valid[1];
-    assign tc_p1_bus_if.rsp_data = tc_d_bits_data[1];
+    assign tc_p1_bus_if.rsp_data.data = tc_d_bits_data[1];
+    assign tc_p1_bus_if.rsp_data.tag = tc_d_bits_tag[1];
     assign tc_d_ready = {tc_p1_bus_if.rsp_ready, tc_p0_bus_if.rsp_ready};
 
     // gbar -------------------------------------------------------------------

hw/rtl/core/VX_core.sv

@@ -420,6 +420,32 @@ module VX_core import VX_gpu_pkg::*; #(
         end
     end
 
+    /*
+    // fake fsm driving tc output
+    reg [15:0] cycles_till_request;
+    always @(posedge clk) begin
+        if (reset) begin
+            cycles_till_request <= 16'd127;
+        end else begin
+            if (cycles_till_request == 0) begin
+                cycles_till_request <= 16'd127;
+            end else begin
+                cycles_till_request <= cycles_till_request - 1;
+            end
+        end
+    end
+    assign tc_p0_bus_if.req_valid = (cycles_till_request == 16'd0);
+    assign tc_p1_bus_if.req_valid = (cycles_till_request == 16'd64);
+    assign tc_p0_bus_if.req_data.addr = 32'hff008100;
+    assign tc_p1_bus_if.req_data.addr = 32'hff018100;
+    assign tc_p0_bus_if.req_data.tag = 4'h0;
+    assign tc_p1_bus_if.req_data.tag = 4'h1;
+    assign tc_p0_bus_if.rsp_ready = 1'b1;
+    assign tc_p1_bus_if.rsp_ready = 1'b1;
+    // `RUNTIME_ASSERT(!tc_p0_bus_if.rsp_data.valid || (tc_p0_bus_if.rsp_data.tag === 4'h0));
+    // `RUNTIME_ASSERT(!tc_p1_bus_if.rsp_data.valid || (tc_p1_bus_if.rsp_data.tag === 4'h1));
+    */
+
     always @(posedge clk) begin
         if (!reset && (busy_negedge || (report_counter == 32'd0))) begin
             $display("====================CORE : %d===================",CORE_ID);

hw/rtl/mem/VX_tc_bus_if.sv

@@ -15,15 +15,18 @@
 
 interface VX_tc_bus_if #(
     parameter DATA_SIZE  = 32,
-    parameter ADDR_WIDTH = `MEM_ADDR_WIDTH
+    parameter ADDR_WIDTH = `MEM_ADDR_WIDTH,
+    parameter TAG_WIDTH = 4
 )();
 
     typedef struct packed {
         logic [ADDR_WIDTH-1:0] addr;
+        logic [TAG_WIDTH-1:0] tag;
     } req_data_t;
 
     typedef struct packed {
         logic [DATA_SIZE*8-1:0] data;
+        logic [TAG_WIDTH-1:0] tag;
     } rsp_data_t;
 
     logic  req_valid;