wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor updates

Browse Source
This commit is contained in:
Blaise Tine
2021-01-18 04:22:40 -08:00
parent 9bce15a513
commit ce9ef840d6
12 changed files with 1714 additions and 3297 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
hw/rtl/VX_config.vh
View File

@@ -108,7 +108,7 @@
`ifdef ALTERA_S10
`define LATENCY_FDIV 34
`else
`define LATENCY_FDIV 20
`define LATENCY_FDIV 15
`endif
`endif
@@ -116,18 +116,10 @@
`ifdef ALTERA_S10
`define LATENCY_FSQRT 25
`else
`define LATENCY_FSQRT 15
`define LATENCY_FSQRT 10
`endif
`endif
`ifndef LATENCY_ITOF
`define LATENCY_ITOF 7
`endif
`ifndef LATENCY_FTOI
`define LATENCY_FTOI 3
`endif
`ifndef LATENCY_FDIVSQRT
`define LATENCY_FDIVSQRT 32
`endif

2850
hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv
View File

File diff suppressed because it is too large Load Diff

2
hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv
View File

@@ -16,7 +16,7 @@
// ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmadd
// SystemVerilog created on Sun Dec 27 09:47:20 2020
// SystemVerilog created on Mon Jan 18 04:15:46 2021
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)

1593
hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv
View File

File diff suppressed because it is too large Load Diff

246
hw/rtl/fp_cores/altera/arria10/acl_gen.log
View File

@@ -4,97 +4,7 @@ argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fadd
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPAdd@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method single path@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fsub
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPSub@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method single path@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fmul
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPMul@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fmadd
Frequency 250MHz
@@ -110,8 +20,8 @@ The pipeline depth of the block is 4 cycle(s)
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@error 1.00@
@rounding NA@
@method multadd@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@@ -125,24 +35,24 @@ argc=23
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fdiv
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3
The pipeline depth of the block is 20 cycle(s)
Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3
The pipeline depth of the block is 15 cycle(s)
@@start
@name FPDiv@
@latency 20@
@LUT 1067@
@DSP 7@
@RAMBits 34304@
@latency 15@
@LUT 539@
@DSP 5@
@RAMBits 32768@
@RAMBlockUsage 3@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@error 1.00@
@rounding NA@
@method polynomial approximation@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@@ -155,142 +65,26 @@ argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fsqrt
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3
The pipeline depth of the block is 15 cycle(s)
Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3
The pipeline depth of the block is 10 cycle(s)
@@start
@name FPSqrt@
@latency 15@
@LUT 518@
@DSP 5@
@latency 10@
@LUT 271@
@DSP 3@
@RAMBits 15872@
@RAMBlockUsage 3@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@error 1.00@
@rounding NA@
@method polynomial approximation@
@inPort 0 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftoi
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 327@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 1@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftou
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 287@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 0@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_itof
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 397@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fxp 32 0 1@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_utof
Frequency 300MHz
Deployment FPGA Arria10
Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 363@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fxp 32 0 0@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end

2
hw/rtl/fp_cores/altera/arria10/acl_gen.sh
View File

@@ -5,7 +5,7 @@ PREFIX=acl
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2"
OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -faithfulRounding -noChanValid -enable -speedgrade 2"
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH