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cache area optimization + IPC boost from 4.24 => 4.42

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This commit is contained in:
Blaise Tine
2021-07-26 21:24:27 -07:00
parent b307c40ae7
commit d2aa228a34
4 changed files with 12 additions and 12 deletions
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18
hw/rtl/VX_config.vh
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@@ -250,7 +250,7 @@
// Core Request Queue Size
`ifndef ICREQ_SIZE
`define ICREQ_SIZE 4
`define ICREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -270,7 +270,7 @@
// Memory Response Queue Size
`ifndef IMRSQ_SIZE
`define IMRSQ_SIZE 4
`define IMRSQ_SIZE 0
`endif
// Dcache Configurable Knobs //////////////////////////////////////////////////
@@ -292,7 +292,7 @@
// Core Request Queue Size
`ifndef DCREQ_SIZE
`define DCREQ_SIZE 4
`define DCREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -312,7 +312,7 @@
// Memory Response Queue Size
`ifndef DMRSQ_SIZE
`define DMRSQ_SIZE `MAX(4, `DNUM_BANKS)
`define DMRSQ_SIZE 0
`endif
// SM Configurable Knobs //////////////////////////////////////////////////////
@@ -334,7 +334,7 @@
// Core Request Queue Size
`ifndef SCREQ_SIZE
`define SCREQ_SIZE 4
`define SCREQ_SIZE 2
`endif
// Core Response Queue Size
@@ -356,7 +356,7 @@
// Core Request Queue Size
`ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 4
`define L2CREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -376,7 +376,7 @@
// Memory Response Queue Size
`ifndef L2MRSQ_SIZE
`define L2MRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2))
`define L2MRSQ_SIZE 0
`endif
// L3cache Configurable Knobs /////////////////////////////////////////////////
@@ -393,7 +393,7 @@
// Core Request Queue Size
`ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 4
`define L3CREQ_SIZE 0
`endif
// Core Response Queue Size
@@ -413,7 +413,7 @@
// Memory Response Queue Size
`ifndef L3MRSQ_SIZE
`define L3MRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2))
`define L3MRSQ_SIZE 0
`endif
`endif

2
hw/rtl/VX_mem_unit.v
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@@ -275,7 +275,7 @@ module VX_mem_unit # (
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
.BUFFERED_REQ (1),
.BUFFERED_RSP (1)
.BUFFERED_RSP (2)
) mem_arb (
.clk (clk),
.reset (reset),

2
hw/rtl/VX_scoreboard.v
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@@ -40,7 +40,7 @@ module VX_scoreboard #(
end
reg [31:0] deadlock_ctr;
wire [31:0] deadlock_timeout = 1000 * (10 ** (`L2_ENABLE + `L3_ENABLE));
wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
always @(posedge clk) begin
if (reset) begin
deadlock_ctr <= 0;

2
hw/rtl/VX_smem_arb.v
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@@ -32,7 +32,7 @@ module VX_smem_arb (
VX_stream_demux #(
.NUM_REQS (2),
.DATAW (REQ_DATAW),
.BUFFERED (1)
.BUFFERED (2)
) req_demux (
.clk (clk),
.reset (reset),