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minor reset delay fix

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This commit is contained in:
Blaise Tine
2021-07-16 21:31:46 -07:00
parent 53b3d42908
commit e0487e4555
4 changed files with 6 additions and 10 deletions
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2
driver/opae/vlsim/opae_sim.cpp
View File

@@ -8,8 +8,6 @@
#define CCI_RQ_SIZE 16
#define CCI_WQ_SIZE 16
#define RESET_DELAY 4
#define ENABLE_MEM_STALLS
#ifndef MEM_LATENCY

2
hw/rtl/VX_config.vh
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@@ -120,6 +120,8 @@
`define LATENCY_FCVT 5
`endif
`define RESET_DELAY 6
// CSR Addresses //////////////////////////////////////////////////////////////
// User Floating-Point CSRs

10
hw/rtl/afu/vortex_afu.sv
View File

@@ -37,8 +37,6 @@ module vortex_afu #(
input avs_readdatavalid [NUM_LOCAL_MEM_BANKS]
);
localparam RESET_DELAY = 3;
localparam LMEM_LINE_WIDTH = $bits(t_local_mem_data);
localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr);
localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt);
@@ -170,7 +168,7 @@ wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid
// disable assertions until full reset
`ifndef VERILATOR
reg [$clog2(RESET_DELAY+1)-1:0] assert_delay_ctr;
reg [$clog2(`RESET_DELAY+1)-1:0] assert_delay_ctr;
initial begin
$assertoff;
end
@@ -179,7 +177,7 @@ always @(posedge clk) begin
assert_delay_ctr <= 0;
end else begin
assert_delay_ctr <= assert_delay_ctr + 1;
if (assert_delay_ctr == RESET_DELAY) begin
if (assert_delay_ctr == (`RESET_DELAY-1)) begin
$asserton; // enable assertions
end
end
@@ -293,7 +291,7 @@ reg cmd_write_done;
wire cmd_run_done;
reg vx_started;
reg [$clog2(RESET_DELAY+1)-1:0] vx_reset_ctr;
reg [$clog2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
always @(posedge clk) begin
if (state == STATE_IDLE) begin
vx_reset_ctr <= 0;
@@ -365,7 +363,7 @@ always @(posedge clk) begin
`endif
end
end else begin
if (vx_reset_ctr == $bits(vx_reset_ctr)'(RESET_DELAY)) begin
if (vx_reset_ctr == (`RESET_DELAY-1)) begin
vx_started <= 1;
vx_reset <= 0;
end

2
hw/simulate/simulator.cpp
View File

@@ -3,8 +3,6 @@
#include <fstream>
#include <iomanip>
#define RESET_DELAY 4
#define ENABLE_MEM_STALLS
#ifndef MEM_LATENCY