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elastic buffers classification

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This commit is contained in:
Blaise Tine
2024-01-31 00:39:37 -08:00
parent b6919d19a7
commit e2d1387df8
6 changed files with 323 additions and 135 deletions
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31
hw/rtl/libs/VX_bypass_buffer.sv
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@@ -11,6 +11,14 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
// A bypass elastic buffer operates at full bandwidth where pop can happen if the buffer is empty but is going full
// It has the following benefits:
// + Full-bandwidth throughput
// + use only one register for storage
// It has the following limitations:
// + data_out is not registered
// + ready_in and ready_out are coupled
`include "VX_platform.vh" `include "VX_platform.vh"
`TRACING_OFF `TRACING_OFF
@@ -35,30 +43,27 @@ module VX_bypass_buffer #(
assign data_out = data_in; assign data_out = data_in;
end else begin end else begin
reg [DATAW-1:0] buffer; reg [DATAW-1:0] buffer;
reg buffer_valid; reg has_data;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
buffer_valid <= 0; has_data <= 0;
end else begin end else begin
if (ready_out) begin if (ready_out) begin
buffer_valid <= 0; has_data <= 0;
end end else if (~has_data) begin
if (valid_in && ~ready_out) begin has_data <= valid_in;
`ASSERT(!buffer_valid, ("runtime error"));
buffer_valid <= 1;
end end
end end
if (~has_data) begin
if (valid_in && ~ready_out) begin
buffer <= data_in; buffer <= data_in;
end end
end end
assign ready_in = ready_out || !buffer_valid; assign ready_in = ready_out || ~has_data;
assign data_out = buffer_valid ? buffer : data_in; assign data_out = has_data ? buffer : data_in;
assign valid_out = valid_in || buffer_valid; assign valid_out = valid_in || has_data;
end end
endmodule endmodule
`TRACING_ON `TRACING_ON

35
hw/rtl/libs/VX_elastic_buffer.sv
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@@ -42,34 +42,33 @@ module VX_elastic_buffer #(
end else if (SIZE == 1) begin end else if (SIZE == 1) begin
wire stall = valid_out && ~ready_out; VX_pipe_buffer #(
.DATAW (DATAW)
VX_pipe_register #( ) pipe_buffer (
.DATAW (1 + DATAW), .clk (clk),
.RESETW (1) .reset (reset),
) pipe_register ( .valid_in (valid_in),
.clk (clk), .data_in (data_in),
.reset (reset), .ready_in (ready_in),
.enable (~stall), .valid_out (valid_out),
.data_in ({valid_in, data_in}), .data_out (data_out),
.data_out ({valid_out, data_out}) .ready_out (ready_out)
); );
assign ready_in = ~stall;
end else if (SIZE == 2) begin end else if (SIZE == 2) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.FULL_BW (OUT_REG != 2),
.OUT_REG (OUT_REG) .OUT_REG (OUT_REG)
) skid_buffer ( ) skid_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.valid_in (valid_in), .valid_in (valid_in),
.data_in (data_in),
.ready_in (ready_in), .ready_in (ready_in),
.data_in (data_in),
.data_out (data_out),
.valid_out (valid_out), .valid_out (valid_out),
.data_out (data_out),
.ready_out (ready_out) .ready_out (ready_out)
); );
@@ -111,10 +110,10 @@ module VX_elastic_buffer #(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.valid_in (~empty), .valid_in (~empty),
.ready_in (ready_out_t),
.data_in (data_out_t), .data_in (data_out_t),
.data_out (data_out), .ready_in (ready_out_t),
.valid_out (valid_out), .valid_out (valid_out),
.data_out (data_out),
.ready_out (ready_out) .ready_out (ready_out)
); );

63
hw/rtl/libs/VX_pipe_buffer.sv Normal file
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@@ -0,0 +1,63 @@
// Copyright 2024 blaise
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// A pipelined elastic buffer operates at full bandwidth where push can happen if the buffer is not empty but is going empty
// It has the following benefits:
// + Full-bandwidth throughput
// + use only one register for storage
// + data_out is fully registered
// It has the following limitations:
// + ready_in and ready_out are coupled
`include "VX_platform.vh"
`TRACING_OFF
module VX_pipe_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
wire stall = valid_out && ~ready_out;
VX_pipe_register #(
.DATAW (1 + DATAW),
.RESETW (1)
) pipe_register (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in, data_in}),
.data_out ({valid_out, data_out})
);
assign ready_in = ~stall;
end
endmodule
`TRACING_ON

131
hw/rtl/libs/VX_skid_buffer.sv
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@@ -17,6 +17,7 @@
module VX_skid_buffer #( module VX_skid_buffer #(
parameter DATAW = 32, parameter DATAW = 32,
parameter PASSTHRU = 0, parameter PASSTHRU = 0,
parameter FULL_BW = 0,
parameter OUT_REG = 0 parameter OUT_REG = 0
) ( ) (
input wire clk, input wire clk,
@@ -30,8 +31,6 @@ module VX_skid_buffer #(
input wire ready_out, input wire ready_out,
output wire valid_out output wire valid_out
); );
`STATIC_ASSERT ((OUT_REG <= 2), ("invalid parameter"))
if (PASSTHRU != 0) begin if (PASSTHRU != 0) begin
`UNUSED_VAR (clk) `UNUSED_VAR (clk)
@@ -41,112 +40,36 @@ module VX_skid_buffer #(
assign data_out = data_in; assign data_out = data_in;
assign ready_in = ready_out; assign ready_in = ready_out;
end else if (OUT_REG == 0) begin end else if (FULL_BW != 0) begin
reg [1:0][DATAW-1:0] shift_reg; VX_stream_buffer #(
reg valid_out_r, ready_in_r, rd_ptr_r; .DATAW (DATAW),
.OUT_REG (OUT_REG)
wire push = valid_in && ready_in; ) stream_buffer (
wire pop = valid_out_r && ready_out; .clk (clk),
.reset (reset),
always @(posedge clk) begin .valid_in (valid_in),
if (reset) begin .data_in (data_in),
valid_out_r <= 0; .ready_in (ready_in),
ready_in_r <= 1; .valid_out (valid_out),
rd_ptr_r <= 1; .data_out (data_out),
end else begin .ready_out (ready_out)
if (push) begin );
if (!pop) begin
ready_in_r <= rd_ptr_r;
valid_out_r <= 1;
end
end else if (pop) begin
ready_in_r <= 1;
valid_out_r <= rd_ptr_r;
end
rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
end
end
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
end
assign ready_in = ready_in_r;
assign valid_out = valid_out_r;
assign data_out = shift_reg[rd_ptr_r];
end else if (OUT_REG == 1) begin
// Full-bandwidth operation: input is consummed every cycle.
// However, data_out register has an additional multiplexer.
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
wire stall_out = valid_out_r && ~ready_out;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end else if (valid_in && valid_out) begin
use_buffer <= 1;
end
if (~stall_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
end
always @(posedge clk) begin
if (push) begin
buffer <= data_in;
end
if (~stall_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
end
assign ready_in = ~use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end else begin end else begin
// Half-bandwidth operation: input is consummed every other cycle. VX_toggle_buffer #(
// However, data_out register has no additional multiplexer. .DATAW (DATAW)
) toggle_buffer (
reg [DATAW-1:0] data_out_r; .clk (clk),
reg has_data; .reset (reset),
.valid_in (valid_in),
always @(posedge clk) begin .data_in (data_in),
if (reset) begin .ready_in (ready_in),
has_data <= 0; .valid_out (valid_out),
end else begin .data_out (data_out),
if (~has_data) begin .ready_out (ready_out)
has_data <= valid_in; );
end else if (ready_out) begin
has_data <= 0;
end
end
if (~has_data) begin
data_out_r <= data_in;
end
end
assign ready_in = ~has_data;
assign valid_out = has_data;
assign data_out = data_out_r;
end end

128
hw/rtl/libs/VX_stream_buffer Normal file
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@@ -0,0 +1,128 @@
// Copyright 2024 blaise
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// A stream elastic buffer operates at full-bandwidth where push and pop can happen simultaneously
// It has the following benefits:
// + full-bandwidth throughput
// + ready_in and ready_out are decoupled
// + data_out can be fully registered
// It has the following limitations:
// - requires two registers for storage
`include "VX_platform.vh"
`TRACING_OFF
module VX_stream_buffer #(
parameter DATAW = 1,
parameter OUT_REG = 0,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
wire stall_out = valid_out_r && ~ready_out;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end else if (valid_in && valid_out) begin
use_buffer <= 1;
end
if (~stall_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
end
always @(posedge clk) begin
if (push) begin
buffer <= data_in;
end
if (~stall_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
end
assign ready_in = ~use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end else begin
reg [1:0][DATAW-1:0] shift_reg;
reg valid_out_r, ready_in_r, rd_ptr_r;
wire push = valid_in && ready_in;
wire pop = valid_out_r && ready_out;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
ready_in_r <= 1;
rd_ptr_r <= 1;
end else begin
if (push) begin
if (!pop) begin
ready_in_r <= rd_ptr_r;
valid_out_r <= 1;
end
end else if (pop) begin
ready_in_r <= 1;
valid_out_r <= rd_ptr_r;
end
rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
end
end
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
end
assign ready_in = ready_in_r;
assign valid_out = valid_out_r;
assign data_out = shift_reg[rd_ptr_r];
end
end
endmodule
`TRACING_ON

70
hw/rtl/libs/VX_toggle_buffer.sv Normal file
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@@ -0,0 +1,70 @@
// Copyright 2024 blaise
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// A toggle elastic buffer operates at half-bandwidth where push can only trigger after pop
// It has the following benefits:
// + use only one register for storage
// + ready_in and ready_out are decoupled
// + data_out is fully registered
// It has the following limitations:
// - Half-bandwidth throughput
`include "VX_platform.vh"
`TRACING_OFF
module VX_toggle_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
if (PASSTHRU != 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign ready_in = ready_out;
assign valid_out = valid_in;
assign data_out = data_in;
end else begin
reg [DATAW-1:0] buffer;
reg has_data;
always @(posedge clk) begin
if (reset) begin
has_data <= 0;
end else begin
if (~has_data) begin
has_data <= valid_in;
end else if (ready_out) begin
has_data <= 0;
end
end
if (~has_data) begin
buffer <= data_in;
end
end
assign ready_in = ~has_data;
assign valid_out = has_data;
assign data_out = buffer;
end
endmodule
`TRACING_ON