refactoring
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@@ -20,14 +20,6 @@ module VX_lsu_unit #(
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output wire delay
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);
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// Generate Addresses
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wire[`NUM_THREADS-1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen (
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.base_address (lsu_req_if.base_address),
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.offset (lsu_req_if.offset),
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.address (address)
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);
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wire[`NUM_THREADS-1:0][31:0] use_address;
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wire[`NUM_THREADS-1:0][31:0] use_store_data;
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wire[`NUM_THREADS-1:0] use_valid;
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@@ -40,6 +32,12 @@ module VX_lsu_unit #(
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genvar i;
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// Generate Full Addresses
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wire[`NUM_THREADS-1:0][31:0] full_address;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign full_address[i] = lsu_req_if.base_address[i] + lsu_req_if.offset;
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end
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VX_generic_register #(
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.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
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) lsu_buffer (
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@@ -47,7 +45,7 @@ module VX_lsu_unit #(
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.reset (reset),
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.stall (delay),
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.flush (1'b0),
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.in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}),
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.in ({full_address,lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}),
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.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
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);
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