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Vector mask changes

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proshan3
2019-11-22 08:07:00 -05:00
parent 6e0b59caa9
commit eb5845e90e
45 changed files with 0 additions and 77590 deletions
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simX/obj_dir/Vcache_simX
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simX/obj_dir/Vcache_simX.cpp
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simX/obj_dir/Vcache_simX.h
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vcache_simX_H_
#define _Vcache_simX_H_
#include "verilated.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_Cache_Bank__pi7;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Anonymous structures to workaround compiler member-count bugs
struct {
CData/*0:0*/ cache_simX__DOT__icache_i_m_ready;
CData/*0:0*/ cache_simX__DOT__dcache_i_m_ready;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__read_or_write;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid;
IData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids;
CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank;
SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank;
SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__state;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found;
};
struct {
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update;
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask;
SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way;
IData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[16];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[16];
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[4];
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr;
IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[4];
QData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[8];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[8];
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f;
IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4];
};
struct {
CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4];
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1];
WData/*7:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32][4];
IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32];
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32];
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32];
WData/*7:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32][4];
IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32];
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32];
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32];
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
CData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1;
CData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2;
SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index;
SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found;
CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use;
CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use;
CData/*3:0*/ __Vtableidx1;
CData/*3:0*/ __Vtableidx2;
CData/*3:0*/ __Vtableidx3;
CData/*3:0*/ __Vtableidx4;
CData/*3:0*/ __Vtableidx5;
CData/*3:0*/ __Vtableidx6;
CData/*3:0*/ __Vtableidx7;
CData/*3:0*/ __Vtableidx8;
CData/*3:0*/ __Vtableidx9;
CData/*0:0*/ __Vclklast__TOP__clk;
CData/*0:0*/ __Vclklast__TOP__reset;
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[16];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[4];
WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[4];
IData/*31:0*/ __Vm_traceActivity;
static CData/*1:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[16];
static CData/*0:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[16];
static IData/*31:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[16];
static CData/*0:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[16];
static IData/*31:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[16];
static CData/*0:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[16];
static IData/*31:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[16];
static CData/*0:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[16];
static IData/*31:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16];
static CData/*0:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16];
static IData/*31:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16];
static CData/*1:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[16];
static CData/*0:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[16];
static IData/*31:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16];
static CData/*1:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[16];
static CData/*0:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[16];
static IData/*31:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16];
static CData/*1:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index[16];
static CData/*0:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found[16];
static IData/*31:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16];
static CData/*1:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[16];
static CData/*0:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[16];
static IData/*31:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16];
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vcache_simX__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vcache_simX); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vcache_simX(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
~Vcache_simX();
/// Trace signals in the model; called by application code
void trace(VerilatedVcdC* tfp, int levels, int options = 0);
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(Vcache_simX__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp);
static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

85
simX/obj_dir/Vcache_simX.mk
View File

@@ -1,85 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vcache_simX.mk
default: Vcache_simX
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vcache_simX
# Module prefix (from --prefix)
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
args \
core \
enc \
instruction \
mem \
simX \
util \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include Vcache_simX_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
args.o: args.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
core.o: core.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
enc.o: enc.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
instruction.o: instruction.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
mem.o: mem.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
simX.o: simX.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
util.o: util.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
# Verilated -*- Makefile -*-

8669
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp
View File

File diff suppressed because it is too large Load Diff

283
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi7.h
View File

@@ -1,283 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_Cache_Bank__pi7_H_
#define _Vcache_simX_VX_Cache_Bank__pi7_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_Cache_Bank__pi7) {
public:
// PORTS
VL_IN8(rst,0,0);
VL_IN8(clk,0,0);
VL_IN8(state,3,0);
VL_IN8(actual_index,4,0);
VL_IN8(block_offset,1,0);
VL_IN8(valid_in,0,0);
VL_IN8(read_or_write,0,0);
VL_IN8(i_p_mem_read,2,0);
VL_IN8(i_p_mem_write,2,0);
VL_IN8(byte_select,1,0);
VL_IN8(evicted_way,0,0);
VL_OUT8(hit,0,0);
VL_OUT8(eviction_wb,0,0);
VL_IN(o_tag,20,0);
VL_IN(writedata,31,0);
VL_INW(fetched_writedata,127,0,4);
VL_OUT(readdata,31,0);
VL_OUT(eviction_addr,31,0);
VL_OUTW(data_evicted,127,0,4);
// LOCAL SIGNALS
CData/*0:0*/ __PVT__valid_use;
CData/*0:0*/ __PVT__access;
CData/*0:0*/ __PVT__write_from_mem;
CData/*0:0*/ __PVT__miss;
CData/*0:0*/ __PVT__way_to_update;
CData/*3:0*/ __PVT__sb_mask;
SData/*3:0*/ __PVT__we;
CData/*0:0*/ __PVT__genblk1__BRA__0__KET____DOT__normal_write;
CData/*0:0*/ __PVT__genblk1__BRA__1__KET____DOT__normal_write;
CData/*0:0*/ __PVT__genblk1__BRA__2__KET____DOT__normal_write;
CData/*0:0*/ __PVT__genblk1__BRA__3__KET____DOT__normal_write;
CData/*1:0*/ __PVT__data_structures__DOT__valid_use_per_way;
CData/*1:0*/ __PVT__data_structures__DOT__dirty_use_per_way;
CData/*1:0*/ __PVT__data_structures__DOT__hit_per_way;
IData/*3:0*/ __PVT__data_structures__DOT__we_per_way;
CData/*1:0*/ __PVT__data_structures__DOT__write_from_mem_per_way;
CData/*0:0*/ __PVT__data_structures__DOT__invalid_found;
CData/*0:0*/ __PVT__data_structures__DOT__way_index;
CData/*0:0*/ __PVT__data_structures__DOT__invalid_index;
CData/*0:0*/ __PVT__data_structures__DOT__way_use_Qual;
CData/*0:0*/ __PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found;
IData/*20:0*/ __PVT__tag_use;
IData/*31:0*/ __PVT__data_unQual;
IData/*31:0*/ __PVT__use_write_data;
WData/*31:0*/ __PVT__data_write[4];
QData/*20:0*/ __PVT__data_structures__DOT__tag_use_per_way;
WData/*31:0*/ __PVT__data_structures__DOT__data_use_per_way[8];
WData/*31:0*/ __PVT__data_structures__DOT__data_write_per_way[8];
IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f;
IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind;
IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f;
IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind;
WData/*7:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32][4];
IData/*20:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32];
CData/*0:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32];
CData/*0:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32];
WData/*7:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32][4];
IData/*20:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32];
CData/*0:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32];
CData/*0:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32];
// LOCAL VARIABLES
// Anonymous structures to workaround compiler member-count bugs
struct {
CData/*0:0*/ data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use;
CData/*0:0*/ data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use;
CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0;
CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32;
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// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vcache_simX_VX_Cache_Bank__pi7); ///< Copying not allowed
public:
Vcache_simX_VX_Cache_Bank__pi7(const char* name = "TOP");
~Vcache_simX_VX_Cache_Bank__pi7();
// API METHODS
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void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
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void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

37
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp
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@@ -1,37 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dcache_request_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dcache_request_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,out_cache_driver_in_address);
out_cache_driver_in_valid = VL_RAND_RESET_I(4);
}

52
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h
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@@ -1,52 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_request_inter_H_
#define _Vcache_simX_VX_dcache_request_inter_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_request_inter) {
public:
// PORTS
// LOCAL SIGNALS
CData/*3:0*/ out_cache_driver_in_valid;
WData/*31:0*/ out_cache_driver_in_address[4];
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vcache_simX_VX_dcache_request_inter); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_request_inter(const char* name = "TOP");
~Vcache_simX_VX_dcache_request_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

36
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp
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@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,i_m_readdata);
}

51
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h
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@@ -1,51 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
public:
// PORTS
// LOCAL SIGNALS
WData/*31:0*/ i_m_readdata[4];
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name = "TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

36
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp
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@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(512,i_m_readdata);
}

51
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h
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@@ -1,51 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
public:
// PORTS
// LOCAL SIGNALS
WData/*31:0*/ i_m_readdata[16];
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name = "TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

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simX/obj_dir/Vcache_simX__ALL.a
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simX/obj_dir/Vcache_simX__ALLcls.cpp
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@@ -1,7 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi7.cpp"

10
simX/obj_dir/Vcache_simX__ALLcls.d
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@@ -1,10 +0,0 @@
Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
Vcache_simX.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi7.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_Cache_Bank__pi7.cpp

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5
simX/obj_dir/Vcache_simX__ALLsup.cpp
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@@ -1,5 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX__Trace.cpp"
#include "Vcache_simX__Syms.cpp"
#include "Vcache_simX__Trace__Slow.cpp"

9
simX/obj_dir/Vcache_simX__ALLsup.d
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@@ -1,9 +0,0 @@
Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h Vcache_simX__Syms.h \
/usr/local/share/verilator/include/verilated.h Vcache_simX.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi7.h \
Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp

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simX/obj_dir/Vcache_simX__ALLsup.o
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47
simX/obj_dir/Vcache_simX__Syms.cpp
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@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi7.h"
// FUNCTIONS
Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
, TOP__cache_simX__DOT__VX_dcache_req(Verilated::catName(topp->name(),"cache_simX.VX_dcache_req"))
, TOP__cache_simX__DOT__VX_dram_req_rsp(Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp"))
, TOP__cache_simX__DOT__VX_dram_req_rsp_icache(Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
}

48
simX/obj_dir/Vcache_simX__Syms.h
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@@ -1,48 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _Vcache_simX__Syms_H_
#define _Vcache_simX__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi7.h"
// SYMS CLASS
class Vcache_simX__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
// SUBCELL STATE
Vcache_simX* TOPp;
Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
~Vcache_simX__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
} VL_ATTR_ALIGNED(64);
#endif // guard

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simX/obj_dir/Vcache_simX__ver.d
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obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi7.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/local/bin/verilator_bin ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/local/bin/verilator_bin cache_simX.v

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simX/obj_dir/Vcache_simX__verFiles.dat
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@@ -1,42 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 283 10696049115265660 1574383273 224134400 1574383273 224134400 "../rtl/VX_countones.v"
S 7236 5066549581052550 1574383273 231079500 1574383273 231079500 "../rtl/VX_define.v"
S 8325 2251799813945994 1574383273 232119600 1574383273 232119600 "../rtl/VX_dmem_controller.v"
S 517 3096224744077973 1574383273 236061300 1574383273 236061300 "../rtl/VX_generic_priority_encoder.v"
S 683 2814749767367343 1574383273 260714600 1574383273 260714600 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 10977524091976397 1574383273 267695600 1574383273 267695600 "../rtl/cache/VX_Cache_Bank.v"
S 748 10977524091976401 1574383273 277789900 1574383273 277789900 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 9851624185133791 1574383273 278740700 1574383273 278740700 "../rtl/cache/VX_cache_data.v"
S 6476 34058472182250218 1574383273 279715700 1574383273 279715700 "../rtl/cache/VX_cache_data_per_index.v"
S 14456 13229323905661682 1574383273 279715700 1574383273 279715700 "../rtl/cache/VX_d_cache.v"
S 393 5910974511184689 1574383273 301972800 1574383273 301972800 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 2814749767367474 1574383273 302974100 1574383273 302974100 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 8725724278291251 1574383273 304006100 1574383273 304006100 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 6192449487895387 1574383273 313939400 1574383273 313939400 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 27021597764483932 1574383273 313939400 1574383273 313939400 "../rtl/interfaces/VX_icache_response_inter.v"
S 7236 5066549581052550 1574383273 231079500 1574383273 231079500 "../rtl/shared_memory/../VX_define.v"
S 676 3940649674211014 1574383273 400242000 1574383273 400242000 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 3096224744079047 1574383273 411240400 1574383273 411240400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 3096224744079048 1574383273 412279700 1574383273 412279700 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 3940649674211020 1574383273 412279700 1574383273 412279700 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5629640 281474978453844 1574044016 334922400 1574044016 333963200 "/usr/local/bin/verilator_bin"
S 3144 1407374883818566 1574383274 742155300 1574383274 742155300 "cache_simX.v"
T 751758 20547673300142630 1574427193 757744700 1574427193 757744700 "obj_dir/Vcache_simX.cpp"
T 31623 7599824371327898 1574427193 691983400 1574427193 691983400 "obj_dir/Vcache_simX.h"
T 2380 7318349394745968 1574427193 846458800 1574427193 846458800 "obj_dir/Vcache_simX.mk"
T 769517 4785074604350062 1574427193 841470700 1574427193 841470700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp"
T 24956 5629499534482029 1574427193 770660800 1574427193 770660800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi7.h"
T 1012 5066549581060716 1574427193 766841100 1574427193 766841100 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1356 4785074604350059 1574427193 765276000 1574427193 765276000 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 987 5348024557771370 1574427193 763679100 1574427193 763679100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
T 1333 5910974511192681 1574427193 761684400 1574427193 761684400 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
T 987 9288674231720551 1574427193 760896800 1574427193 760896800 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1334 20829148276857269 1574427193 759408000 1574427193 759408000 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 3838 54606145481948840 1574427193 527314200 1574427193 527314200 "obj_dir/Vcache_simX__Syms.cpp"
T 1968 41939771530004893 1574427193 528311300 1574427193 528311300 "obj_dir/Vcache_simX__Syms.h"
T 762929 82472168176354735 1574427193 687881900 1574427193 687881900 "obj_dir/Vcache_simX__Trace.cpp"
T 990142 253046004063004355 1574427193 619067200 1574427193 619067200 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1444 8444249301588593 1574427193 847454700 1574427193 847454700 "obj_dir/Vcache_simX__ver.d"
T 0 0 1574427193 858425500 1574427193 858425500 "obj_dir/Vcache_simX__verFiles.dat"
T 1489 13792273859091055 1574427193 843885600 1574427193 843885600 "obj_dir/Vcache_simX_classes.mk"

47
simX/obj_dir/Vcache_simX_classes.mk
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vcache_simX.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_Cache_Bank__pi7 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
Vcache_simX__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vcache_simX__Syms \
Vcache_simX__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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simX/obj_dir/args.d
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args.o: ../args.cpp ../include/args.h

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simX/obj_dir/core.d
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core.o: ../core.cpp ../include/types.h ../include/util.h \
../include/types.h ../include/archdef.h ../include/mem.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/archdef.h ../include/enc.h \
../include/asm-tokens.h ../include/core.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilated.h ../include/debug.h

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simX/obj_dir/emulator.debug
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5
simX/obj_dir/enc.d
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enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/archdef.h \
../include/enc.h ../include/asm-tokens.h ../include/archdef.h \
../include/instruction.h

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simX/obj_dir/instruction.d
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instruction.o: ../instruction.cpp ../include/instruction.h \
../include/types.h ../include/trace.h ../include/obj.h \
../include/archdef.h ../include/instruction.h ../include/enc.h \
../include/obj.h ../include/asm-tokens.h ../include/core.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilated.h ../include/harpfloat.h \
../include/debug.h

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simX/obj_dir/mem.d
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mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/mem.h ../include/core.h \
../include/archdef.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/asm-tokens.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilated.h

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simX/obj_dir/simX.d
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simX.o: ../simX.cpp ../include/debug.h ../include/types.h \
../include/core.h ../include/types.h ../include/archdef.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/asm-tokens.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilated.h ../include/enc.h \
../include/instruction.h ../include/mem.h ../include/obj.h \
../include/archdef.h ../include/args.h ../include/help.h

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simX/obj_dir/util.d
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util.o: ../util.cpp ../include/types.h ../include/util.h \
../include/types.h

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8
simX/obj_dir/verilated.d
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verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

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4
simX/obj_dir/verilated_vcd_c.d
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verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h

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