fixed simulator leak
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@@ -11,7 +11,7 @@ double sc_time_stamp() {
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Simulator::Simulator() {
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// force random values for unitialized signals
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Verilated::randReset(2);
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Verilated::randReset(1);
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// Turn off assertion before reset
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Verilated::assertOn(false);
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@@ -105,9 +105,8 @@ void Simulator::eval_dram_bus() {
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if (!dram_rsp_active_) {
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if (dequeue_index != -1) {
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vortex_->dram_rsp_valid = 1;
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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free(dram_rsp_vec_[dequeue_index].data);
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].block.data(), GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
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dram_rsp_active_ = true;
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} else {
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@@ -141,9 +140,8 @@ void Simulator::eval_dram_bus() {
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} else {
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dram_req_t dram_req;
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dram_req.cycles_left = DRAM_LATENCY;
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dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
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dram_req.tag = vortex_->dram_req_tag;
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ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
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ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
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dram_rsp_vec_.push_back(dram_req);
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}
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}
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@@ -21,7 +21,7 @@
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typedef struct {
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int cycles_left;
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uint8_t *data;
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std::array<uint8_t, GLOBAL_BLOCK_SIZE> block;
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unsigned tag;
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} dram_req_t;
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