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fixed unsued parameters warnings

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This commit is contained in:
Blaise Tine
2021-03-02 16:20:36 -05:00
parent 88d5cd4979
commit fdfc8e9605
35 changed files with 94 additions and 73 deletions
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3
driver/opae/vlsim/verilator.vlt
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@@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule UNUSED -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule LITENDIAN -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule IMPORTSTAR -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*"

2
driver/opae/vlsim/vortex_afu_shim.sv
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@@ -1,5 +1,5 @@
`include "vortex_afu.vh"
`include "VX_define.vh"
`include "vortex_afu.vh"
/* verilator lint_off IMPORTSTAR */
import ccip_if_pkg::*;
import local_mem_cfg_pkg::*;

3
driver/rtlsim/verilator.vlt
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@@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"
lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*"

5
hw/rtl/VX_alu_unit.v
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@@ -12,7 +12,10 @@ module VX_alu_unit #(
// Outputs
VX_branch_ctl_if branch_ctl_if,
VX_commit_if alu_commit_if
);
);
`UNUSED_PARAM (CORE_ID)
reg [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] add_result;
wire [`NUM_THREADS-1:0][32:0] sub_result;

12
hw/rtl/VX_core.v
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@@ -73,27 +73,23 @@ module VX_core #(
VX_dcache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_rsp_if();
VX_icache_core_req_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_req_if();
VX_icache_core_rsp_if #(
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_rsp_if();
VX_pipeline #(

3
hw/rtl/VX_decode.v
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@@ -15,9 +15,10 @@ module VX_decode #(
VX_wstall_if wstall_if,
VX_join_if join_if
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
reg [`EX_BITS-1:0] ex_type;
reg [`OP_BITS-1:0] op_type;
reg [`MOD_BITS-1:0] op_mod;

2
hw/rtl/VX_fpu_unit.v
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@@ -17,6 +17,8 @@ module VX_fpu_unit #(
input wire[`NUM_WARPS-1:0] csr_pending,
output wire[`NUM_WARPS-1:0] pending
);
`UNUSED_PARAM (CORE_ID)
localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);
wire ready_in;

2
hw/rtl/VX_gpr_stage.v
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@@ -13,6 +13,8 @@ module VX_gpr_stage #(
// outputs
VX_gpr_rsp_if gpr_rsp_if
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset)
// ensure r0 never gets written, which can happen before the reset

2
hw/rtl/VX_gpu_unit.v
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@@ -15,6 +15,8 @@ module VX_gpu_unit #(
VX_warp_ctl_if warp_ctl_if,
VX_commit_if gpu_commit_if
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)

3
hw/rtl/VX_ibuffer.v
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@@ -13,6 +13,9 @@ module VX_ibuffer #(
// outputs
VX_decode_if ibuf_deq_if
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS;
localparam SIZE = 3;
localparam ADDRW = $clog2(SIZE);

2
hw/rtl/VX_icache_stage.v
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@@ -18,6 +18,8 @@ module VX_icache_stage #(
// reponse
VX_ifetch_rsp_if ifetch_rsp_if
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset)
wire icache_req_fire = icache_req_if.valid && icache_req_if.ready;

2
hw/rtl/VX_lsu_unit.v
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@@ -20,6 +20,8 @@ module VX_lsu_unit #(
VX_commit_if st_commit_if
);
`UNUSED_PARAM (CORE_ID)
wire req_valid;
wire [`NUM_THREADS-1:0] req_tmask;
wire [`NUM_THREADS-1:0][31:0] req_addr;

28
hw/rtl/VX_mem_unit.v
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@@ -41,31 +41,27 @@ module VX_mem_unit # (
) dcache_dram_rsp_if(), icache_dram_rsp_if();
VX_dcache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) dcache_rsp_if();
VX_dcache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) smem_req_if();
VX_dcache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH)
) smem_rsp_if();
VX_databus_arb databus_arb (

12
hw/rtl/VX_pipeline.v
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@@ -63,8 +63,7 @@ module VX_pipeline #(
VX_dcache_core_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_req_if();
assign dcache_req_valid = dcache_core_req_if.valid;
@@ -82,8 +81,7 @@ module VX_pipeline #(
VX_dcache_core_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH)
) dcache_core_rsp_if();
assign dcache_core_rsp_if.valid = dcache_rsp_valid;
@@ -97,8 +95,7 @@ module VX_pipeline #(
VX_icache_core_req_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_req_if();
assign icache_req_valid = icache_core_req_if.valid;
@@ -112,8 +109,7 @@ module VX_pipeline #(
VX_icache_core_rsp_if #(
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH)
) icache_core_rsp_if();
assign icache_core_rsp_if.valid = icache_rsp_valid;

4
hw/rtl/VX_platform.vh
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@@ -33,6 +33,10 @@
/* verilator lint_on DECLFILENAME */ \
/* verilator lint_on IMPLICIT */
`define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \
localparam __``x = x; \
/* verilator lint_on UNUSED */
`define UNUSED_VAR(x) always @(x) begin end
`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \

3
hw/rtl/VX_warp_sched.v
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@@ -18,6 +18,9 @@ module VX_warp_sched #(
output wire busy
);
`UNUSED_PARAM (CORE_ID)
wire join_fall;
wire [31:0] join_pc;
wire [`NUM_THREADS-1:0] join_tm;

3
hw/rtl/VX_writeback.v
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@@ -15,6 +15,9 @@ module VX_writeback #(
// outputs
VX_writeback_if writeback_if
);
`UNUSED_PARAM (CORE_ID)
wire ld_valid = ld_commit_if.valid && ld_commit_if.wb;
wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;

7
hw/rtl/afu/vortex_afu.sv
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@@ -1,5 +1,5 @@
`include "VX_define.vh"
`ifndef NOPAE
`include "platform_if.vh"
import local_mem_cfg_pkg::*;
`include "afu_json_info.vh"
`else
@@ -10,8 +10,6 @@ import local_mem_cfg_pkg::*;
/* verilator lint_on IMPORTSTAR */
`endif
`include "VX_define.vh"
module vortex_afu #(
parameter NUM_LOCAL_MEM_BANKS = 2
) (
@@ -993,6 +991,9 @@ VX_scope #(
.bus_write(cmd_scope_write)
);
`else
`UNUSED_PARAM (MMIO_SCOPE_READ)
`UNUSED_PARAM (MMIO_SCOPE_WRITE)
`endif
endmodule

4
hw/rtl/afu/vortex_afu.vh
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@@ -1,14 +1,18 @@
`ifndef __VORTEX_AFU__
`define __VORTEX_AFU__
`IGNORE_WARNINGS_BEGIN
`include "ccip_if_pkg.sv"
`IGNORE_WARNINGS_END
`define PLATFORM_PROVIDES_LOCAL_MEMORY
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
`IGNORE_WARNINGS_BEGIN
`include "local_mem_cfg_pkg.sv"
`IGNORE_WARNINGS_END
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c

7
hw/rtl/cache/VX_bank.v vendored
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@@ -22,8 +22,6 @@ module VX_bank #(
parameter CREQ_SIZE = 1,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 1,
// DRAM Response Queue Size
parameter DRSQ_SIZE = 1,
// DRAM Request Queue Size
parameter DREQ_SIZE = 1,
@@ -92,6 +90,8 @@ module VX_bank #(
input wire [`LINE_SELECT_BITS-1:0] flush_addr
);
`UNUSED_PARAM (CORE_TAG_ID_BITS)
`ifdef DBG_CACHE_REQ_INFO
/* verilator lint_off UNUSED */
wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1;
@@ -420,8 +420,7 @@ module VX_bank #(
VX_miss_resrv #(
.BANK_ID (BANK_ID),
.CACHE_ID (CACHE_ID),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.CACHE_ID (CACHE_ID),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.NUM_PORTS (NUM_PORTS),

6
hw/rtl/cache/VX_cache.v vendored
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@@ -163,10 +163,9 @@ module VX_cache #(
///////////////////////////////////////////////////////////////////////////
VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_SIZE (CACHE_SIZE),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE)
.NUM_BANKS (NUM_BANKS)
) flush_ctrl (
.clk (clk),
.reset (reset),
@@ -294,7 +293,6 @@ module VX_cache #(
.NUM_REQS (NUM_REQS),
.CREQ_SIZE (CREQ_SIZE),
.MSHR_SIZE (MSHR_SIZE),
.DRSQ_SIZE (DRSQ_SIZE),
.DREQ_SIZE (DREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),

4
hw/rtl/cache/VX_data_access.v vendored
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@@ -38,6 +38,10 @@ module VX_data_access #(
input wire [CACHE_LINE_SIZE-1:0] byteen,
input wire [`CACHE_LINE_WIDTH-1:0] wdata
);
`UNUSED_PARAM (CACHE_ID)
`UNUSED_PARAM (BANK_ID)
`UNUSED_PARAM (WORD_SIZE)
`UNUSED_VAR (reset)
`UNUSED_VAR (readen)

4
hw/rtl/cache/VX_flush_ctrl.v vendored
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@@ -6,9 +6,7 @@ module VX_flush_ctrl #(
// Size of line inside a bank in bytes
parameter CACHE_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 1
parameter NUM_BANKS = 1
) (
input wire clk,
input wire reset,

6
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -19,9 +19,7 @@ module VX_miss_resrv #(
parameter MSHR_SIZE = 1,
parameter ALM_FULL = (MSHR_SIZE-1),
// core request tag size
parameter CORE_TAG_WIDTH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
parameter CORE_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
@@ -58,6 +56,8 @@ module VX_miss_resrv #(
// dequeue
input wire dequeue
);
`UNUSED_PARAM (CACHE_ID)
`UNUSED_PARAM (BANK_ID)
localparam ADDRW = $clog2(MSHR_SIZE);
reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;

2
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -49,6 +49,8 @@ module VX_shared_mem #(
);
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
`UNUSED_PARAM (CACHE_ID)
`UNUSED_PARAM (CORE_TAG_ID_BITS)
localparam CACHE_LINE_SIZE = WORD_SIZE;

3
hw/rtl/cache/VX_tag_access.v vendored
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@@ -31,6 +31,9 @@ module VX_tag_access #(
input wire is_flush,
output wire tag_match
);
`UNUSED_PARAM (CACHE_ID)
`UNUSED_PARAM (BANK_ID)
`UNUSED_VAR (reset)
`UNUSED_VAR (lookup)

7
hw/rtl/interfaces/VX_dcache_core_req_if.v
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@@ -4,10 +4,9 @@
`include "../cache/VX_cache_config.vh"
interface VX_dcache_core_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;

7
hw/rtl/interfaces/VX_dcache_core_rsp_if.v
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@@ -4,10 +4,9 @@
`include "../cache/VX_cache_config.vh"
interface VX_dcache_core_rsp_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;

5
hw/rtl/interfaces/VX_icache_core_req_if.v
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@@ -4,9 +4,8 @@
`include "../cache/VX_cache_config.vh"
interface VX_icache_core_req_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire valid;

5
hw/rtl/interfaces/VX_icache_core_rsp_if.v
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@@ -4,9 +4,8 @@
`include "../cache/VX_cache_config.vh"
interface VX_icache_core_rsp_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire valid;

1
hw/rtl/libs/VX_dp_ram.v
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@@ -8,7 +8,6 @@ module VX_dp_ram #(
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (

1
hw/rtl/libs/VX_fixed_arbiter.v
View File

@@ -14,6 +14,7 @@ module VX_fixed_arbiter #(
output wire grant_valid
);
`UNUSED_PARAM (LOCK_ENABLE)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)

3
hw/rtl/libs/VX_skid_buffer.v
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@@ -4,8 +4,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter BUFFERED = 0,
parameter FASTRAM = 1
parameter BUFFERED = 0
) (
input wire clk,
input wire reset,

1
hw/rtl/libs/VX_sp_ram.v
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@@ -8,7 +8,6 @@ module VX_sp_ram #(
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (

3
hw/simulate/verilator.vlt
View File

@@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*"
lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*"
lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*"
lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*"
lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*"
lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*"