felsabbagh3
|
01efe02e8b
|
CACHE WORKING just needs lb/sb
|
2019-10-25 03:03:09 -04:00 |
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felsabbagh3
|
1e648c5819
|
FIxed first circular issue
|
2019-10-24 10:38:04 -04:00 |
|
felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
|
2019-10-22 06:02:08 -04:00 |
|
felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
felsabbagh3
|
1bfafca896
|
Cleanup before integration
|
2019-10-22 03:03:17 -04:00 |
|
felsabbagh3
|
0672389edc
|
fix
|
2019-10-21 12:16:17 -04:00 |
|
felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
|
felsabbagh3
|
629ed3f8f9
|
Before ISA2.0
|
2019-10-18 04:15:34 -04:00 |
|
felsabbagh3
|
559c64cb36
|
Cleanup
|
2019-10-18 02:20:38 -04:00 |
|
felsabbagh3
|
505bbc20c8
|
Removed FWD
|
2019-10-18 02:01:39 -04:00 |
|
felsabbagh3
|
95047fcadc
|
Rename Stage that removes the need for forwarding
|
2019-10-17 00:48:54 -04:00 |
|
felsabbagh3
|
ee83e6d8c8
|
Moved GPR to back-end
|
2019-10-14 19:08:32 -04:00 |
|
felsabbagh3
|
fb3bc60189
|
Finalized GPR with 3-Port Structure
|
2019-09-11 14:53:32 -04:00 |
|
felsabbagh3
|
ecf81336db
|
Finished FE and BE high-level
|
2019-09-08 19:28:53 -04:00 |
|
felsabbagh3
|
981bf0afe5
|
FE Done
|
2019-09-08 18:36:47 -04:00 |
|
felsabbagh3
|
ad45758a35
|
Before Fetch->FE
|
2019-09-08 18:09:11 -04:00 |
|
felsabbagh3
|
c310e7381f
|
Icache interface
|
2019-09-08 17:36:09 -04:00 |
|
felsabbagh3
|
5e6804703f
|
Decode in FE
|
2019-09-08 17:24:51 -04:00 |
|
felsabbagh3
|
ac9b06bf7d
|
Before FE BE abstraction
|
2019-09-08 16:21:37 -04:00 |
|
felsabbagh3
|
fe09aafbb4
|
Interface Checkpoint 2 - Remove Lints
|
2019-09-05 19:32:37 -04:00 |
|
felsabbagh3
|
2d0e41db63
|
checkpoint: Added icache struct
|
2019-09-03 16:19:06 -04:00 |
|
felsabbagh3
|
d7afef04a9
|
Sim Work miss
|
2019-05-18 23:42:55 +04:00 |
|
felsabbagh3
|
48468ed26a
|
Proper SIMT with fine-grain scheduler implemented
|
2019-05-10 00:49:54 -07:00 |
|
felsabbagh3
|
96dac5e1ce
|
Warp + Context Aware Design - Global Stalling
|
2019-05-08 16:32:49 -07:00 |
|
felsabbagh3
|
a6c13bc38c
|
Inefficient context aware desgin
|
2019-05-08 15:55:06 -07:00 |
|
felsabbagh3
|
f21eaec79f
|
Provisioned SM
|
2019-04-05 19:25:54 -04:00 |
|
felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
|
2019-03-31 05:02:55 -04:00 |
|
felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:09:03 -04:00 |
|
felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
|
2019-03-30 03:54:20 -04:00 |
|
felsabbagh3
|
d02c3d25b7
|
sync
|
2019-03-27 13:52:13 -04:00 |
|
felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
|
2019-03-27 03:53:59 -04:00 |
|
felsabbagh3
|
9b42e79dcf
|
Added HW threads - Infinite loop
|
2019-03-27 03:44:14 -04:00 |
|
felsabbagh3
|
cc0fb0eece
|
better use of valid signal
|
2019-03-27 00:07:59 -04:00 |
|
felsabbagh3
|
7a528c5ef2
|
Packing data wires + ALU module
|
2019-03-26 19:17:11 -04:00 |
|