Lingjun Zhu
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0ad491f20e
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Added dc.log
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2019-11-11 14:30:14 -05:00 |
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felsabbagh3
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4b2ea58b79
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Syn prep
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2019-11-11 14:20:15 -05:00 |
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felsabbagh3
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7863175233
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Set associative bank working
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2019-10-30 14:57:20 -04:00 |
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Lingjun Zhu
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3609742707
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Finished synthesis at 1GHz, cell count increases to 1870k
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2019-10-29 11:33:23 -04:00 |
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Lingjun Zhu
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3c6f0b5d15
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Included the SDC and DDC files
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2019-10-28 17:24:19 -04:00 |
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Lingjun Zhu
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fa5b476874
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Added the synthesis netlist
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2019-10-28 17:11:15 -04:00 |
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Lingjun Zhu
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0d8a7be5c6
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Finished synthesis with optimization
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2019-10-28 17:10:30 -04:00 |
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Lingjun Zhu
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b6558714ca
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Finished synthesis with all memory but no optimization
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2019-10-28 16:18:11 -04:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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Lingjun Zhu
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50d567d70c
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Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
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2019-10-28 14:49:55 -04:00 |
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felsabbagh3
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557c987bb0
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Updated files list
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2019-10-28 14:29:07 -04:00 |
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felsabbagh3
|
28ee1d3c36
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Sucess Synthesis - Finding db
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2019-10-28 13:52:49 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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8013708a5b
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Added fsyn for my synthesis
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2019-10-27 22:16:57 -04:00 |
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felsabbagh3
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6fda88b68f
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Modelsim Makefile compile + simulate - DPI
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2019-10-26 19:01:49 -04:00 |
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felsabbagh3
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de8de00f6e
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Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
|
b4d921f49a
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set_top_level tcl
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2019-10-23 11:56:32 -04:00 |
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felsabbagh3
|
3cb5820ecd
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-10-22 13:19:00 -04:00 |
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felsabbagh3
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f68942c92a
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Added cache+shared memory search path
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2019-10-22 13:18:49 -04:00 |
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Shim
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c43b3800d8
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added report power and save ddc to synthesis script
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2019-10-22 11:27:13 -04:00 |
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felsabbagh3
|
9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
|
1bfafca896
|
Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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Lingjun Zhu
|
eeb0a321a8
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Finished synthesis with no optimization, cell count increasts to 100k
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2019-10-21 17:53:51 -04:00 |
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Lingjun Zhu
|
e2cd8102eb
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Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing
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2019-10-21 17:09:51 -04:00 |
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felsabbagh3
|
fd876144f5
|
.tcl mod
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2019-10-21 11:27:01 -04:00 |
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felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
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felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
|
f7b55427b4
|
Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
|
559c64cb36
|
Cleanup
|
2019-10-18 02:20:38 -04:00 |
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felsabbagh3
|
505bbc20c8
|
Removed FWD
|
2019-10-18 02:01:39 -04:00 |
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felsabbagh3
|
ccbb2acab5
|
LSU+EXU minor
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2019-10-17 22:38:09 -04:00 |
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felsabbagh3
|
6779d0fade
|
Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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Lingjun Zhu
|
d164ebfbc6
|
Added log file of synthesis, too many registers are removed
|
2019-10-17 14:25:54 -04:00 |
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Lingjun Zhu
|
a4d6ada16d
|
Fixed the issues of memory during synthesis
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2019-10-17 14:18:52 -04:00 |
|
Shim
|
78e4067013
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added log file
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2019-10-17 14:00:22 -04:00 |
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Shim
|
0bea82a2c3
|
added tcl file
|
2019-10-17 11:55:18 -04:00 |
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