Blaise Tine
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1f63139ce5
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fix RTL code undefined variables
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2020-04-03 22:59:40 -07:00 |
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felsabbagh3
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10e445d459
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Provisioned Prefetching, currently disabled
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2020-04-03 00:30:33 -07:00 |
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felsabbagh3
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7d1cc5234e
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Fixed dram_fill_accept dependant on input address
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2020-04-02 20:26:37 -07:00 |
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felsabbagh3
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0e0b326b31
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Removed bank Hazard Signals
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2020-04-02 19:19:00 -07:00 |
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felsabbagh3
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1b9d9f3625
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Fixed incorrect miss_add on pipeline stall
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2020-03-31 20:23:09 -07:00 |
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felsabbagh3
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bcf894b581
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Demo SOC W=8, T=4 Passing
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2020-03-30 22:17:38 -07:00 |
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felsabbagh3
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66a837b0df
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SOC only 2 errors
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2020-03-30 21:28:40 -07:00 |
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felsabbagh3
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36895d6e7c
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Fixed miss_add on for snoop replays
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2020-03-29 21:21:53 -07:00 |
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felsabbagh3
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94cc2c10b1
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Snoops shouldn't send fill requests
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2020-03-29 19:16:00 -07:00 |
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felsabbagh3
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e31b2d6d7e
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Fixed pulling signals from different stages
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2020-03-29 18:17:01 -07:00 |
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felsabbagh3
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d31116d584
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Uses use_wb_valid instead of wb_req to include snoops
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2020-03-29 17:59:10 -07:00 |
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felsabbagh3
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71aae3e0a9
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..
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2020-03-29 17:28:57 -07:00 |
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felsabbagh3
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f96d77d75e
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Mismatched vs matched
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2020-03-29 17:18:57 -07:00 |
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felsabbagh3
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a499bcd718
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Added extra signals for debugging
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2020-03-29 17:04:17 -07:00 |
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felsabbagh3
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95ee66f25a
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Fixed Snoop Invalidate Logic
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2020-03-29 16:44:14 -07:00 |
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felsabbagh3
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73390b9f58
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b/unb error
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2020-03-29 16:09:48 -07:00 |
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felsabbagh3
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0a88c97485
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Another reset issue...
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2020-03-29 16:06:13 -07:00 |
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felsabbagh3
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eb6e0cee43
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Fixing a bug in a fix...
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2020-03-29 13:52:22 -07:00 |
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felsabbagh3
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cd418a1f96
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Mrvq stopping reqq popping added to avoid mrvq full deadlock
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2020-03-29 13:19:06 -07:00 |
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felsabbagh3
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f43a9ad1a6
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Added proper resetting to cache
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2020-03-29 10:57:32 -07:00 |
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felsabbagh3
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efac643c66
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Added Proper Handshaking to Everything and Fixed a Couple of Bugs
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2020-03-29 02:11:14 -07:00 |
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felsabbagh3
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313a8e3b4b
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All cache bugs fixed - Handshaking
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2020-03-28 21:43:02 -07:00 |
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felsabbagh3
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5dc9493c61
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ALL tests passing - handshake
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2020-03-27 21:34:49 -07:00 |
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felsabbagh3
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614797e52f
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Migrating fpga_synthesis_temp to main
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2020-03-27 13:15:23 -07:00 |
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Blaise Tine
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9621acff5b
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fixed Modelsim build errors
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2020-03-26 03:54:23 -04:00 |
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felsabbagh3
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4e6de0dc38
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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d146070275
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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wgulian3
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b1e77bec44
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replace procedural continuous assignments and force MLAB inference for generic_queue_ll
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2020-03-10 17:46:48 -04:00 |
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wgulian3
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372a1ad905
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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felsabbagh3
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13c6cbfa5d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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cf0173ae15
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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e2ffbcf14b
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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b5b04a7070
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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507d20f413
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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f03f3fe037
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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felsabbagh3
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9bf0add937
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
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fb23812e95
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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44f6c68fe9
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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Blaise Tine
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0816426662
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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9f5235dc3d
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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9c56a10f15
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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33868512ac
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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66a46f81ce
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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457e8644f3
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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e0620a6f6a
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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b0b9b8238e
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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a47f7c11ec
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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8ece8d8893
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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80af320fdb
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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