Blaise Tine
|
1f63139ce5
|
fix RTL code undefined variables
|
2020-04-03 22:59:40 -07:00 |
|
felsabbagh3
|
10e445d459
|
Provisioned Prefetching, currently disabled
|
2020-04-03 00:30:33 -07:00 |
|
felsabbagh3
|
e31b2d6d7e
|
Fixed pulling signals from different stages
|
2020-03-29 18:17:01 -07:00 |
|
felsabbagh3
|
d31116d584
|
Uses use_wb_valid instead of wb_req to include snoops
|
2020-03-29 17:59:10 -07:00 |
|
felsabbagh3
|
efac643c66
|
Added Proper Handshaking to Everything and Fixed a Couple of Bugs
|
2020-03-29 02:11:14 -07:00 |
|
felsabbagh3
|
e2ffbcf14b
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
felsabbagh3
|
507d20f413
|
Cache Working on Mem Copy
|
2020-03-08 01:55:15 -08:00 |
|
felsabbagh3
|
9bf0add937
|
Made the cache module configurable for multi-instantiation
|
2020-03-07 00:49:40 -08:00 |
|
Blaise Tine
|
33868512ac
|
synthesis fixes
|
2020-03-05 07:03:23 -05:00 |
|
Blaise Tine
|
66a46f81ce
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
felsabbagh3
|
457e8644f3
|
Added Snoop Invalidate/Writeback Req type
|
2020-03-05 01:30:16 -08:00 |
|
felsabbagh3
|
b0b9b8238e
|
Passing some cases
|
2020-03-04 04:05:54 -08:00 |
|
felsabbagh3
|
80af320fdb
|
Before fixing miss rsrv for ST->LD sequences
|
2020-03-03 16:57:05 -08:00 |
|
felsabbagh3
|
fc5621cd1d
|
Everything except bank internals
|
2020-03-02 23:08:54 -08:00 |
|