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Author SHA1 Message Date
wgulian3 e145b8078c fix shared mem ram inference 2020-02-20 15:59:23 -05:00
wgulian3 55d722364d Merge branch 'fpga_synthesis' into fix_cache_m10k 2020-02-20 02:36:39 -05:00
wgulian3 2d3b790324 Merge branch 'fpga_synthesis' into fix_cache_m10k 2020-02-20 02:36:39 -05:00
codetector e82e29c855 remove async reset for FPGA synthesis 2020-02-19 23:19:05 -05:00
codetector e901fb6a3a remove async reset for FPGA synthesis 2020-02-19 23:19:05 -05:00
wgulian3 de85cfd296 fix clean build with makefile 2020-02-19 17:33:51 -05:00
Codetector 072c89c433 Merge branch 'fpga_synthesis' into fix_cache_m10k 2020-02-19 16:03:23 -05:00
Codetector 1a29007bc7 Merge branch 'fpga_synthesis' into fix_cache_m10k 2020-02-19 16:03:23 -05:00
wgulian3 5dadeffac8 fix project.tcl 2020-02-19 14:20:58 -05:00
wgulian3 3b60c10460 Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis 2020-02-19 01:04:55 -05:00
wgulian3 3423e3189f Fix e2e building issues and increase division pipeline length 2020-02-19 01:04:48 -05:00
wgulian3 3e68c8bcf5 verilator does not support delayed assignment in a loop 2020-02-18 13:38:17 -05:00
wgulian3 e76d05f7ce Fix issues quartus synthesis issues 2020-02-18 13:24:18 -05:00
wgulian3 d71f8fcc73 Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu. 2020-02-18 13:02:46 -05:00
wgulian3 a32d654263 Merge branch 'master' into fpga_synthesis 2020-02-18 03:35:12 -05:00
wgulian3 61803741f8 Merge branch 'master' into fpga_synthesis 
# Conflicts:
#	rtl/VX_back_end.v
#	rtl/VX_gpr_stage.v
#	rtl/VX_writeback.v
#	rtl/simulate/test_bench.cpp
#	rtl/simulate/test_bench.h
#	runtime/mains/dev/Makefile
 2020-02-18 03:34:38 -05:00
felsabbagh3 28ce40eebf fixed make w + vx_gpr_stage csr schedule 2020-02-18 00:26:44 -08:00
felsabbagh3 be66e51613 Added CSRs, some Load unit tests are failing 2020-02-17 22:22:27 -08:00
felsabbagh3 a0f3f67426 Fixed double printing in ::io_handler 2020-02-17 19:47:55 -08:00
felsabbagh3 551c4aa2e9 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-02-17 19:36:17 -08:00
felsabbagh3 3a45375596 Fixed Verilator 2020-02-17 19:36:00 -08:00
Blaise Tine 3aa4c26eb9 minor fix 2020-02-17 20:36:16 -05:00
Blaise Tine 90c3813340 fixed all C++ extra + pedantic errors 2020-02-17 15:02:06 -05:00
wgulian3 4184980188 verilator: run all riscv tests 2020-02-13 13:50:57 -05:00
wgulian3 e662ef4134 Fix verilator 2020-02-13 13:42:43 -05:00
wgulian3 86bfa4d1e4 Fix verilator 2020-02-13 13:18:06 -05:00
wgulian3 8318aff69f Support exec multi-cycle for div/mul 2020-02-13 13:17:46 -05:00
codetector ded06bcd12 ram m10k fix 2020-02-11 09:57:32 -05:00
codetector f1673726b2 ram m10k fix 2020-02-11 09:57:32 -05:00
wgulian3 c1bd731d7f Add ram async clear port fix for fpga RAM inference 2020-02-06 13:07:50 -05:00
wgulian3 9c7a9d88cf Replace div/rem expressions with divider modules in preparation for pipelining 2020-02-04 11:54:06 -05:00
wgulian3 0211ca4add Add compat divide module and tb 2020-02-04 10:59:05 -05:00
wgulian3 8d20b52ea2 Cleanup imports of VX_define 2020-02-04 10:57:32 -05:00
Elsabbagh, Fares Ehab Mohamed AbouelnasrandGitHub Enterprise 0e0ea52568 Merge pull request #1 from casl/OPAE 
opae
 2020-01-30 13:45:05 -08:00
Apurve Chawda 2eed4e68be Create opae_setup.sh 2020-01-30 16:41:37 -05:00
Tine, BlaiseandGitHub Enterprise cd07b508fa Update README.md 2020-01-29 15:39:33 -05:00
wgulian3 d727404f3b timing analysis tcl 2020-01-28 04:09:00 -05:00
wgulian3 4158b29f29 Fancier SDC file 2020-01-28 02:20:13 -05:00
wgulian3 a6e74f589e Update files 2020-01-27 20:35:45 -05:00
Tine, BlaiseandGitHub Enterprise ca283f39eb Update README.md 2020-01-27 03:42:36 -05:00
Tine, BlaiseandGitHub Enterprise 9b66bb4ed4 Update README.md 2020-01-27 01:46:31 -05:00
wgulian3andWilliam Gulian 12a4136464 quartus makefile: Support custom Quartus root location 2020-01-24 18:42:03 -05:00
wgulian3 e9cdc6e5af SystemVerilog tweaks to appease Quartus and make Quartus synthesis work 2020-01-24 06:10:24 -05:00
Blaise Tine 229d76ff23 update 2020-01-22 00:56:03 -05:00
Blaise Tine 383bc15794 update 2020-01-22 00:49:23 -05:00
Blaise Tine df435ffa97 update README 2020-01-22 00:47:57 -05:00
Blaise Tine 43d5612a6b updated README 2020-01-21 21:23:00 -05:00
Blaise Tine 759349f2bf updated README and Makefile environment settings 2020-01-21 21:21:56 -05:00
Tine, BlaiseandGitHub Enterprise 60f0cfe215 Create LICENSE 2020-01-11 11:00:37 -05:00
Tine, BlaiseandGitHub Enterprise db3a9e4f73 Update README.md 2020-01-11 10:59:46 -05:00