Cleanup imports of VX_define

rtl/VX_generic_priority_encoder.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "VX_define.v"
 
 module VX_generic_priority_encoder
   #(

rtl/VX_priority_encoder_w_mask.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "VX_define.v"
 module VX_priority_encoder_w_mask
   #(
   	parameter N = 10

rtl/VX_warp.v

@@ -20,8 +20,8 @@ module VX_warp (
 );
 
 		reg[31:0] real_PC;
-		var[31:0] temp_PC;
-		var[31:0] use_PC;
+		logic [31:0] temp_PC;
+		logic [31:0] use_PC;
 		reg[`NT_M1:0] valid;
 
 		reg[`NT_M1:0] valid_zero;

rtl/Vortex.v

@@ -1,5 +1,5 @@
 
-`include "../VX_define.v"
+`include "VX_define.v"
 
 
 module Vortex

rtl/cache/VX_Cache_Bank.v

@@ -2,7 +2,7 @@
 //        Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
 //        Also make sure all possible output states are transmitted back to the bank correctly
 
-`include "../VX_define.v"
+`include "VX_define.v"
 // `include "VX_cache_data.v"
 
 

rtl/cache/VX_cache_bank_valid.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "VX_define.v"
 
 module VX_cache_bank_valid
 #(

rtl/cache/VX_cache_data.v

@@ -1,6 +1,6 @@
 
 
-`include "../VX_define.v"
+`include "VX_define.v"
 
 module VX_cache_data
     #(

rtl/cache/VX_cache_data_per_index.v

@@ -1,6 +1,6 @@
 
 
-`include "../VX_define.v"
+`include "VX_define.v"
 
 module VX_cache_data_per_index
     #(

rtl/cache/VX_d_cache.v

@@ -8,7 +8,7 @@
 // TO DO:
 //   - Send in a response from memory of what the data is from the test bench
 
-`include "../VX_define.v"
+`include "VX_define.v"
 //`include "VX_priority_encoder.v"
 // `include "VX_Cache_Bank.v"
 //`include "cache_set.v"

rtl/cache/VX_d_cache_encapsulate.v

@@ -1,7 +1,7 @@
 
 `include "VX_define.v"
 
-// `define NUM_WORDS_PER_BLOCK 4
+`define NUM_WORDS_PER_BLOCK 4
 
 module VX_d_cache_encapsulate (
 		clk,

rtl/interfaces/VX_frE_to_bckE_req_inter.v

@@ -1,5 +1,5 @@
 
-`include "../VX_define.v"
+`include "VX_define.v"
 
 `ifndef VX_FrE_to_BE_INTER