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Author SHA1 Message Date
felsabbagh3 28ee1d3c36 Sucess Synthesis - Finding db 2019-10-28 13:52:49 -04:00
felsabbagh3 a8d063e9ad Synthesis Cleanup 1 2019-10-28 13:43:12 -04:00
felsabbagh3 88eab9e746 Removed dependancy on 2019-10-27 22:30:32 -04:00
felsabbagh3 8013708a5b Added fsyn for my synthesis 2019-10-27 22:16:57 -04:00
felsabbagh3 1b7f28273b Removed -O3 from makefile 2019-10-27 20:34:32 -04:00
felsabbagh3 0ee74bc566 migrated 100% to modelsim 2019-10-27 20:08:44 -04:00
felsabbagh3 715982cca7 Modelsim Working + Simulating + dumping - Some bugs 2019-10-27 03:36:02 -04:00
felsabbagh3 372c81d90c Generate VCD with ModelSim 2019-10-26 19:35:21 -04:00
felsabbagh3 6fda88b68f Modelsim Makefile compile + simulate - DPI 2019-10-26 19:01:49 -04:00
felsabbagh3 ad46194d1b fixed width 2019-10-26 00:39:27 -04:00
felsabbagh3 1181af1df2 Modelsim basic sim 2019-10-26 00:34:57 -04:00
Elsabbagh 9110e8367e modelsim 2019-10-25 23:41:34 -04:00
felsabbagh3 667dbfbbe8 Trying icarus 2019-10-25 22:54:02 -04:00
felsabbagh3 820007ae80 NUM_REQ 2019-10-25 13:46:31 -04:00
felsabbagh3 c85c01e082 Parametized cache 2019-10-25 13:36:06 -04:00
felsabbagh3 89d0390965 CACHE FINALLY WORKING 2019-10-25 04:01:23 -04:00
felsabbagh3 01efe02e8b CACHE WORKING just needs lb/sb 2019-10-25 03:03:09 -04:00
felsabbagh3 1e648c5819 FIxed first circular issue 2019-10-24 10:38:04 -04:00
felsabbagh3 de8de00f6e Finished cache not tested 2019-10-23 19:07:26 -04:00
felsabbagh3 6340ffcc2a new cache states 2019-10-23 15:07:14 -04:00
felsabbagh3 b4d921f49a set_top_level tcl 2019-10-23 11:56:32 -04:00
felsabbagh3 1645a04b1d Fixed SM + added def SYN 2019-10-22 15:56:30 -04:00
felsabbagh3 3cb5820ecd Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2019-10-22 13:19:00 -04:00
felsabbagh3 f68942c92a Added cache+shared memory search path 2019-10-22 13:18:49 -04:00
Shim c43b3800d8 added report power and save ddc to synthesis script 2019-10-22 11:27:13 -04:00
felsabbagh3 9d8273afe4 Finished Cache Integration 2019-10-22 06:02:08 -04:00
felsabbagh3 b7af8c3f34 Integrated Shared Memory 2019-10-22 05:03:47 -04:00
felsabbagh3 1bfafca896 Cleanup before integration 2019-10-22 03:03:17 -04:00
felsabbagh3 b3f464dd89 Barriers impl + tested 2019-10-22 01:47:39 -04:00
felsabbagh3 31d3d51392 WSPAWN imp + tested 2019-10-21 23:35:53 -04:00
felsabbagh3 c21e400f9f Readded IPDOM stack + SPLIT/Join tested 2019-10-21 21:26:21 -04:00
felsabbagh3 b6375e76de Readded IPDOM stack + SPLIT/Join tested 2019-10-21 21:24:49 -04:00
Lingjun Zhu eeb0a321a8 Finished synthesis with no optimization, cell count increasts to 100k 2019-10-21 17:53:51 -04:00
Lingjun Zhu e2cd8102eb Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing 2019-10-21 17:09:51 -04:00
felsabbagh3 0672389edc fix 2019-10-21 12:16:17 -04:00
felsabbagh3 ce49e2f223 proper init warp scheduelr 2019-10-21 12:13:34 -04:00
felsabbagh3 8050419511 added begin 2019-10-21 12:06:10 -04:00
felsabbagh3 85004899bd added reset to ws 2019-10-21 12:03:07 -04:00
felsabbagh3 99586279d9 always fix stack 2019-10-21 11:49:10 -04:00
felsabbagh3 292c792339 generic stack reset 2019-10-21 11:45:51 -04:00
felsabbagh3 4bfdbb5188 reset posedge 2019-10-21 11:34:12 -04:00
felsabbagh3 fd876144f5 .tcl mod 2019-10-21 11:27:01 -04:00
felsabbagh3 49b139d512 fix 2019-10-21 11:24:45 -04:00
felsabbagh3 121a985d12 Reset to Generic Register 2019-10-21 11:21:13 -04:00
felsabbagh3 bab1852a99 Added Split/Join - not tested 2019-10-21 03:03:15 -04:00
felsabbagh3 84f5ccb484 Added CSR TID/WID reads 2019-10-21 02:10:05 -04:00
Lingjun Zhu 405926f66f Generated memory blocks for data cache (data), data cache (tag), shared memory 2019-10-20 14:52:28 -04:00
felsabbagh3 797801ebae CENA/CENB Modifications + Still not working 2019-10-19 14:52:57 -04:00
Lingjun Zhu 93531715bb Created a testbench and simulated the read/write of the register file 2019-10-18 22:55:34 -04:00
felsabbagh3 4cae140ac1 Mem technology compiling but still reading all zeros 2019-10-18 16:45:42 -04:00