Blaise Tine
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42e3b6c45d
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fixed lmp_mult parameters, ram init filepath
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2020-09-04 07:51:46 -07:00 |
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Blaise Tine
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af84e01856
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minor update
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2020-08-31 06:17:49 -07:00 |
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Blaise Tine
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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Blaise Tine
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efbe4a07ef
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serial divider optimization
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2020-08-25 03:23:57 -07:00 |
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Blaise Tine
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ee81e81818
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adding using serial divider to save area cost
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2020-08-25 02:29:27 -07:00 |
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Blaise Tine
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f292e5003d
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quartus build fixes
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2020-08-23 22:04:46 -07:00 |
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Blaise Tine
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1c9445745f
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fp_noncomp fixes
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2020-08-23 16:53:28 -07:00 |
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Blaise Tine
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96f5432592
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minor update
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2020-08-22 13:56:07 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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65415d2bbc
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getting dogfood tests passing on Verilator!
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2020-08-09 18:13:12 -04:00 |
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Blaise Tine
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cd29362d10
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fixed FPU handshake, optimized writeback's critical path
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2020-08-07 10:11:54 -07:00 |
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Blaise Tine
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ffd9515881
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added altera fpu modules
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2020-08-05 15:53:59 -07:00 |
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Blaise Tine
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d8bdaa2b4e
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minor update
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2020-08-01 14:38:31 -07:00 |
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Blaise Tine
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31ee824862
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merged fpu_port branch
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2020-07-31 17:13:22 -04:00 |
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Blaise Tine
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4bdab8903e
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merge
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2020-07-31 16:49:59 -04:00 |
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Blaise Tine
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27e95530ef
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pipeline optimization
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2020-07-30 03:06:01 -07:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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Blaise Tine
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f3721c523f
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minor update
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2020-07-28 06:02:32 -04:00 |
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Blaise Tine
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7c86b68977
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pipeline refactoring: centralized issue buffer
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2020-07-26 11:21:08 -04:00 |
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Blaise Tine
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dc7efbcfb4
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pipeline refactoring
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2020-07-21 05:22:47 -04:00 |
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Blaise Tine
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25f66e6490
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pipeline refactoring
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2020-07-19 05:03:47 -04:00 |
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trmontgomery
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ed3a0cfa4d
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added rsp map
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2020-07-19 00:08:09 -04:00 |
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Blaise Tine
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bdfacf709c
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yosys synthesis refactoring
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2020-07-10 18:56:41 -04:00 |
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Blaise Tine
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5d088d67c8
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Gather FPGA perf stats
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2020-07-01 09:30:12 -07:00 |
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Blaise Tine
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75d66dc335
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fix sources.txt, run_ase.sh
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2020-06-29 12:52:28 -07:00 |
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Blaise Tine
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a70562d386
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set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18
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2020-06-29 08:03:19 -07:00 |
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felsabbagh3
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e919e452b9
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-06-28 20:01:49 -07:00 |
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felsabbagh3
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21566cdcd7
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Fixed Single Core with Optimizations
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2020-06-28 19:38:36 -07:00 |
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Blaise Tine
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eb67788bf2
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-06-28 14:45:01 -07:00 |
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Blaise Tine
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27ea36440e
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multiplier fixes
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2020-06-28 14:39:18 -07:00 |
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felsabbagh3
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ffb760cf73
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Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter
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2020-06-28 14:27:47 -07:00 |
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Blaise Tine
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baf7d3bb92
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minor update
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2020-06-27 17:46:45 -04:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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e6cc221a44
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refactoring
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2020-06-23 10:59:30 -07:00 |
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Blaise Tine
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0a01385a2c
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few updates
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2020-06-23 09:28:24 -07:00 |
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Blaise Tine
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d3440de403
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round robin arbiter + auto buffered queue + fixed dcache arbiter
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2020-06-20 17:56:04 -04:00 |
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Blaise Tine
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68d9fc9a75
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driver basic test and demo test refactoring
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2020-06-19 09:12:07 -07:00 |
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Blaise Tine
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9850a1f890
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minor fixes
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2020-06-15 00:20:56 -07:00 |
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Blaise Tine
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75af29febb
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scope refactoring
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2020-06-13 11:47:28 -07:00 |
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Blaise Tine
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d6b0ef2b3c
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scope refactoring + snoop invalidate
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2020-06-12 00:04:31 -07:00 |
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Blaise Tine
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19f263c772
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scope fixes
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2020-06-09 20:49:36 -07:00 |
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Blaise Tine
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457783322b
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scope fixes
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2020-06-09 07:03:52 -07:00 |
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Blaise Tine
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9575fe9a51
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scope fixes
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2020-06-08 06:54:47 -07:00 |
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Blaise Tine
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170c88f295
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scope fixes
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2020-06-08 04:25:28 -07:00 |
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Blaise Tine
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9ae38433fb
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VX_pipeline refactoring + logic analyzer
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2020-06-06 01:52:44 -04:00 |
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Blaise Tine
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9eb0389717
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minor update
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2020-06-03 06:40:25 -04:00 |
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Blaise Tine
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04fc34b848
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minor update
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2020-06-03 03:05:45 -07:00 |
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Blaise Tine
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e01c411b20
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opae rtl fixes
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2020-06-01 23:06:13 -07:00 |
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Blaise Tine
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9e5885b820
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adding dram writeenable support + scheduler bug fixes
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2020-05-27 19:00:23 -04:00 |
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