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minor update

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This commit is contained in:
Blaise Tine
2020-06-27 17:46:45 -04:00
parent bc0c65dce7
commit baf7d3bb92
5 changed files with 4 additions and 36 deletions
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2
driver/opae/scope.cpp
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@@ -87,8 +87,6 @@ static const scope_signal_t scope_signals[] = {
{ 1, "scope_bank_is_mrvq_st1" },
{ 1, "scope_bank_miss_st1" },
{ 1, "scope_bank_dirty_st1" },
{ 1, "scope_bank_tag_valid_st1" },
{ 1, "scope_bank_tag_match_st1" },
{ 1, "scope_bank_force_miss_st1" },
///////////////////////////////////////////////////////////////////////////

16
hw/rtl/VX_scope.vh
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@@ -50,8 +50,6 @@
scope_bank_is_mrvq_st1, \
scope_bank_miss_st1, \
scope_bank_dirty_st1, \
scope_bank_tag_valid_st1, \
scope_bank_tag_match_st1, \
scope_bank_force_miss_st1,
@@ -159,8 +157,6 @@
wire scope_bank_is_mrvq_st1; \
wire scope_bank_miss_st1; \
wire scope_bank_dirty_st1; \
wire scope_bank_tag_valid_st1; \
wire scope_bank_tag_match_st1; \
wire scope_bank_force_miss_st1; \
wire scope_bank_stall_pipe;
@@ -202,8 +198,6 @@
output wire scope_bank_is_mrvq_st1, \
output wire scope_bank_miss_st1, \
output wire scope_bank_dirty_st1, \
output wire scope_bank_tag_valid_st1, \
output wire scope_bank_tag_match_st1, \
output wire scope_bank_force_miss_st1, \
output wire scope_bank_stall_pipe,
@@ -272,8 +266,6 @@
.scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \
.scope_bank_miss_st1 (scope_bank_miss_st1), \
.scope_bank_dirty_st1 (scope_bank_dirty_st1), \
.scope_bank_tag_valid_st1 (scope_bank_tag_valid_st1), \
.scope_bank_tag_match_st1 (scope_bank_tag_match_st1), \
.scope_bank_force_miss_st1 (scope_bank_force_miss_st1), \
.scope_bank_stall_pipe (scope_bank_stall_pipe),
@@ -288,8 +280,6 @@
.scope_bank_is_mrvq_st1 (), \
.scope_bank_miss_st1 (), \
.scope_bank_dirty_st1 (), \
.scope_bank_tag_valid_st1 (), \
.scope_bank_tag_match_st1 (), \
.scope_bank_force_miss_st1 (), \
.scope_bank_stall_pipe (), \
/* verilator lint_on PINCONNECTEMPTY */
@@ -305,8 +295,6 @@
wire [NUM_BANKS-1:0] scope_per_bank_is_mrvq_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_dirty_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_tag_valid_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_tag_match_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_force_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_stall_pipe; \
/* verilator lint_on UNUSED */ \
@@ -319,8 +307,6 @@
assign scope_bank_is_mrvq_st1 = scope_per_bank_is_mrvq_st1[0]; \
assign scope_bank_miss_st1 = scope_per_bank_miss_st1[0]; \
assign scope_bank_dirty_st1 = scope_per_bank_dirty_st1[0]; \
assign scope_bank_tag_valid_st1 = scope_per_bank_tag_valid_st1[0]; \
assign scope_bank_tag_match_st1 = scope_per_bank_tag_match_st1[0]; \
assign scope_bank_force_miss_st1 = scope_per_bank_force_miss_st1[0]; \
assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
@@ -334,8 +320,6 @@
.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
.scope_bank_tag_valid_st1 (scope_per_bank_tag_valid_st1[i]), \
.scope_bank_tag_match_st1 (scope_per_bank_tag_match_st1[i]), \
.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),

10
hw/rtl/cache/VX_bank.v vendored
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@@ -412,9 +412,6 @@ module VX_bank #(
wire mrvq_recover_ready_state_st1e;
wire[`LINE_ADDR_WIDTH-1:0] addr_st1e;
wire tag_valid_st1e;
wire tag_match_st1e;
assign is_mrvq_st1e = is_mrvq_st1[STAGE_1_CYCLES-1];
assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1];
assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1];
@@ -476,10 +473,7 @@ module VX_bank #(
.dirtyb_st1e (dirtyb_st1e),
.fill_saw_dirty_st1e (fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e),
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e),
.tag_valid_st1e (tag_valid_st1e),
.tag_match_st1e (tag_match_st1e)
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
);
`ifdef DBG_CORE_REQ_INFO
@@ -764,8 +758,6 @@ module VX_bank #(
`SCOPE_ASSIGN(scope_bank_is_mrvq_st1, is_mrvq_st1e);
`SCOPE_ASSIGN(scope_bank_miss_st1, miss_st1e);
`SCOPE_ASSIGN(scope_bank_dirty_st1, dirty_st1e);
`SCOPE_ASSIGN(scope_bank_tag_valid_st1, tag_valid_st1e);
`SCOPE_ASSIGN(scope_bank_tag_match_st1, tag_match_st1e);
`SCOPE_ASSIGN(scope_bank_force_miss_st1, force_request_miss_st1e);
`SCOPE_ASSIGN(scope_bank_stall_pipe, stall_bank_pipe);

8
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -50,10 +50,7 @@ module VX_tag_data_access #(
output wire[BANK_LINE_SIZE-1:0] dirtyb_st1e,
output wire fill_saw_dirty_st1e,
output wire snp_to_mrvq_st1e,
output wire mrvq_init_ready_state_st1e,
output wire tag_valid_st1e,
output wire tag_match_st1e
output wire mrvq_init_ready_state_st1e
);
wire read_valid_st1c[STAGE_1_CYCLES-1:0];
@@ -197,9 +194,6 @@ module VX_tag_data_access #(
assign fill_saw_dirty_st1e = real_writefill && dirty_st1e;
assign invalidate_line = snoop_hit_no_pending;
assign tag_valid_st1e = use_read_valid_st1e;
assign tag_match_st1e = tags_match;
endmodule

4
hw/rtl/libs/VX_divide.v
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@@ -58,8 +58,8 @@ module VX_divide #(
end
else if (clken) begin
if (i == 0) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
numer_pipe[0] <= numer;
denom_pipe[0] <= denom;
end else begin
numer_pipe[i] <= numer_pipe[i-1];
denom_pipe[i] <= denom_pipe[i-1];