Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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def6a35693
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shared memory optimization
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2020-11-29 15:04:31 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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af2bb3b789
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cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!
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2020-11-05 03:49:50 -08:00 |
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Blaise Tine
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4c6a74fa87
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cache refactoring - phase 3 - added dedicated pipeline stage for tag access
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2020-11-04 03:21:30 -08:00 |
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Blaise Tine
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3fe31fc337
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fixed afu to cpu mempcy hang
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2020-10-28 14:19:13 -07:00 |
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Blaise Tine
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9a9f7955f0
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basic test timing + scope tracing ccip
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2020-10-27 17:04:04 -04:00 |
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Blaise Tine
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58b8e82908
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scope fixes ...
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2020-10-13 17:09:22 -04:00 |
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Blaise Tine
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4bfc4ee78f
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scope fixes
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2020-10-13 08:44:55 -07:00 |
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Blaise Tine
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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Blaise Tine
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309dd48fc6
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scope bug fixes
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2020-10-06 03:59:27 -04:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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df711986bc
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FPU DPI fallback
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2020-08-31 09:19:55 -04:00 |
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Blaise Tine
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b8cd3b0b28
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gpr pipeline optimization
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2020-08-01 12:38:30 -04:00 |
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Blaise Tine
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d79e36912f
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fix opae build
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2020-04-20 12:51:42 -07:00 |
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Blaise Tine
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b76f8696bd
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removing *.vh file for opae build
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2020-04-20 15:07:27 -04:00 |
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Blaise Tine
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31f906f9fd
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fixed all build warnings
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2020-04-16 10:22:46 -04:00 |
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Blaise Tine
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81745f08c9
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added config.vh
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2020-04-16 07:49:19 -04:00 |
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