Blaise Tine
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80f62e8a41
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instruction buffer optimization
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2021-08-02 19:54:28 -07:00 |
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dc34c5c5bd
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minor update
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2021-07-03 04:47:19 -07:00 |
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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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a3a7239b4d
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critical path optimizations
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2021-06-23 01:51:23 -07:00 |
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65a3704479
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minor update
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2021-06-18 01:18:31 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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bd40e7db70
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minor update - mux reordering to reduce critical path on input data
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2021-03-21 11:43:57 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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Blaise Tine
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62ff97d6e1
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minor update - smem perf update
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2021-02-01 10:29:20 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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fa5592be22
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minor updates
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2021-01-12 03:10:39 -08:00 |
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Blaise Tine
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9f128085d5
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scoreboard optimization - using writeback's end-of-packet status
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2020-12-30 06:47:56 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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b459192dec
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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97739e9dcf
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RAM blocks inference fixes
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2020-11-30 14:02:47 -08:00 |
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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a1fcdd467a
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reset networks optimization
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2020-11-16 01:12:02 -08:00 |
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Blaise Tine
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fceb561cbd
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synchronous reset network optimization: only reset register when required
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2020-11-11 20:54:54 -08:00 |
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Blaise Tine
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7529f72c5d
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fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
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2020-10-20 05:32:55 -07:00 |
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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Blaise Tine
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36ec603d17
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fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt
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2020-09-08 07:05:26 -07:00 |
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Blaise Tine
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49b86c4b2a
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SCOPE update
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2020-09-05 10:52:59 -07:00 |
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Blaise Tine
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af84e01856
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minor update
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2020-08-31 06:17:49 -07:00 |
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Blaise Tine
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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Blaise Tine
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fde3f46798
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ibuffer optimization
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2020-08-26 04:44:36 -07:00 |
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Blaise Tine
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ee81e81818
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adding using serial divider to save area cost
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2020-08-25 02:29:27 -07:00 |
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Blaise Tine
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57971f6c76
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decode op_mod optimization
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2020-08-24 02:55:14 -07:00 |
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Blaise Tine
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f292e5003d
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quartus build fixes
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2020-08-23 22:04:46 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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