Blaise Tine
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5c40422e4f
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dcache response bus optimization
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2021-07-12 10:14:48 -07:00 |
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Blaise Tine
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c6afc35989
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adding data fence support
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2021-06-28 06:12:18 -07:00 |
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Blaise Tine
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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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Blaise Tine
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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Blaise Tine
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3cc1190cd7
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CSRs I/O refactoring
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2021-06-11 03:08:07 -07:00 |
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Blaise Tine
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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Blaise Tine
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10a994d11a
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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Blaise Tine
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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9f128085d5
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scoreboard optimization - using writeback's end-of-packet status
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2020-12-30 06:47:56 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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fe07ca9aee
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minor update
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2020-12-09 05:49:02 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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fb60d0af87
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decoupled load/store commits
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2020-12-03 15:08:48 -08:00 |
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Blaise Tine
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f3b1069ce8
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adding stream arbiter
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2020-12-03 06:40:23 -08:00 |
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Blaise Tine
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ac1883a13f
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tabs cleanup
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2020-11-28 17:08:01 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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2e0f51af80
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fixed instr/cycle perf counter
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2020-11-12 11:41:25 -08:00 |
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Blaise Tine
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b14007f930
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pipeline optimization: fixed GPR fanout delay to execute units
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2020-11-07 02:01:21 -08:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Blaise Tine
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807ce24e94
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fixed committed instrs count
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2020-09-08 07:54:12 -07:00 |
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Blaise Tine
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49b86c4b2a
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SCOPE update
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2020-09-05 10:52:59 -07:00 |
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Blaise Tine
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0a0b28aac0
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minor update - 206-214 mhz
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2020-08-29 05:14:08 -07:00 |
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Blaise Tine
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b211b29670
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removing pipeline additional registers
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2020-08-25 14:02:35 -07:00 |
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Blaise Tine
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df25bae456
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optimize warp_sched
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2020-08-24 05:36:00 -07:00 |
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Blaise Tine
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57971f6c76
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decode op_mod optimization
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2020-08-24 02:55:14 -07:00 |
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Blaise Tine
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f292e5003d
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quartus build fixes
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2020-08-23 22:04:46 -07:00 |
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Blaise Tine
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1c9445745f
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fp_noncomp fixes
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2020-08-23 16:53:28 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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65415d2bbc
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getting dogfood tests passing on Verilator!
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2020-08-09 18:13:12 -04:00 |
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Blaise Tine
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cd29362d10
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fixed FPU handshake, optimized writeback's critical path
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2020-08-07 10:11:54 -07:00 |
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Blaise Tine
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ffd9515881
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added altera fpu modules
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2020-08-05 15:53:59 -07:00 |
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Blaise Tine
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b8cd3b0b28
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gpr pipeline optimization
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2020-08-01 12:38:30 -04:00 |
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Blaise Tine
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836a735555
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minor updates
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2020-07-31 13:39:52 -07:00 |
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Blaise Tine
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c9755a0c48
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lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
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Blaise Tine
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27e95530ef
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pipeline optimization
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2020-07-30 03:06:01 -07:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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