Blaise Tine
|
7e4399e3ac
|
OPAE HW full redesign - basic test passing
|
2020-04-02 05:10:51 -04:00 |
|
felsabbagh3
|
7b4b44e5ab
|
Fixed DRAM random latency simulator
|
2020-03-31 20:33:45 -07:00 |
|
felsabbagh3
|
1b9d9f3625
|
Fixed incorrect miss_add on pipeline stall
|
2020-03-31 20:23:09 -07:00 |
|
Blaise Tine
|
bca5ac5e7f
|
enable rtl sim dram stalls
|
2020-03-31 02:41:14 -04:00 |
|
Blaise Tine
|
e92c4b6774
|
enable rtl sim dram stalls
|
2020-03-31 02:38:18 -04:00 |
|
felsabbagh3
|
ba8bc95c90
|
Newlib update
|
2020-03-30 23:08:38 -07:00 |
|
felsabbagh3
|
bcf894b581
|
Demo SOC W=8, T=4 Passing
|
2020-03-30 22:17:38 -07:00 |
|
felsabbagh3
|
66a837b0df
|
SOC only 2 errors
|
2020-03-30 21:28:40 -07:00 |
|
felsabbagh3
|
88f2ad53d0
|
Fixed simulator includes
|
2020-03-30 16:43:26 -07:00 |
|
Blaise Tine
|
f6eb5dfbae
|
refactor RTL sim, added DRAM stalls support
|
2020-03-30 04:13:19 -04:00 |
|
felsabbagh3
|
638625184f
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-29 23:46:44 -07:00 |
|
felsabbagh3
|
ff2b8dba12
|
Fixed req_addr width
|
2020-03-29 23:46:38 -07:00 |
|
Blaise Tine
|
0f39d0fcbd
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-30 01:53:53 -04:00 |
|
Blaise Tine
|
2eb19e23c2
|
refactor RTL simulator
|
2020-03-30 01:53:34 -04:00 |
|
felsabbagh3
|
ccc65a06fe
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-29 21:22:08 -07:00 |
|
felsabbagh3
|
36895d6e7c
|
Fixed miss_add on for snoop replays
|
2020-03-29 21:21:53 -07:00 |
|
Blaise Tine
|
2d198a32c7
|
update
|
2020-03-29 23:18:26 -04:00 |
|
felsabbagh3
|
94cc2c10b1
|
Snoops shouldn't send fill requests
|
2020-03-29 19:16:00 -07:00 |
|
felsabbagh3
|
e31b2d6d7e
|
Fixed pulling signals from different stages
|
2020-03-29 18:17:01 -07:00 |
|
felsabbagh3
|
d31116d584
|
Uses use_wb_valid instead of wb_req to include snoops
|
2020-03-29 17:59:10 -07:00 |
|
felsabbagh3
|
71aae3e0a9
|
..
|
2020-03-29 17:28:57 -07:00 |
|
felsabbagh3
|
f96d77d75e
|
Mismatched vs matched
|
2020-03-29 17:18:57 -07:00 |
|
felsabbagh3
|
a499bcd718
|
Added extra signals for debugging
|
2020-03-29 17:04:17 -07:00 |
|
felsabbagh3
|
95ee66f25a
|
Fixed Snoop Invalidate Logic
|
2020-03-29 16:44:14 -07:00 |
|
felsabbagh3
|
73390b9f58
|
b/unb error
|
2020-03-29 16:09:48 -07:00 |
|
felsabbagh3
|
0a88c97485
|
Another reset issue...
|
2020-03-29 16:06:13 -07:00 |
|
felsabbagh3
|
b99ba2c413
|
Removed scheduler_empty qualifier
|
2020-03-29 15:24:50 -07:00 |
|
felsabbagh3
|
eb6e0cee43
|
Fixing a bug in a fix...
|
2020-03-29 13:52:22 -07:00 |
|
felsabbagh3
|
cd418a1f96
|
Mrvq stopping reqq popping added to avoid mrvq full deadlock
|
2020-03-29 13:19:06 -07:00 |
|
felsabbagh3
|
f43a9ad1a6
|
Added proper resetting to cache
|
2020-03-29 10:57:32 -07:00 |
|
Blaise Tine
|
3a23e05a88
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-29 05:24:48 -04:00 |
|
Blaise Tine
|
ce0cc44d11
|
update
|
2020-03-29 05:24:40 -04:00 |
|
felsabbagh3
|
2c75b7e800
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-29 02:11:23 -07:00 |
|
felsabbagh3
|
efac643c66
|
Added Proper Handshaking to Everything and Fixed a Couple of Bugs
|
2020-03-29 02:11:14 -07:00 |
|
Blaise Tine
|
ede41dff1b
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-29 01:17:32 -04:00 |
|
Blaise Tine
|
c57de94b5c
|
minor update
|
2020-03-29 01:17:09 -04:00 |
|
felsabbagh3
|
d31b607e01
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-03-28 21:43:51 -07:00 |
|
felsabbagh3
|
313a8e3b4b
|
All cache bugs fixed - Handshaking
|
2020-03-28 21:43:02 -07:00 |
|
Blaise Tine
|
002d8fbec9
|
minor update
|
2020-03-29 00:40:02 -04:00 |
|
Blaise Tine
|
c8a6470595
|
redesigned driver demo, fixed startup code, removed --cpu from simx,
|
2020-03-29 00:38:17 -04:00 |
|
Blaise Tine
|
2d5cf89e00
|
update
|
2020-03-28 02:40:38 -04:00 |
|
Blaise Tine
|
17625e7709
|
update
|
2020-03-28 01:43:26 -04:00 |
|
Blaise Tine
|
22be51b0c8
|
fixed multicore build
|
2020-03-28 01:40:26 -04:00 |
|
Blaise Tine
|
cff762c435
|
adding opencl runtime and compiler tools
|
2020-03-28 00:35:54 -04:00 |
|
felsabbagh3
|
5dc9493c61
|
ALL tests passing - handshake
|
2020-03-27 21:34:49 -07:00 |
|
Blaise Tine
|
f7e0d1e491
|
missing runtime changes from OPAE
|
2020-03-27 22:51:54 -04:00 |
|
Blaise Tine
|
96e960fa69
|
missing runtime changes from OPAE
|
2020-03-27 22:51:54 -04:00 |
|
Blaise Tine
|
89d5bfbef1
|
missing simX changes from OPAE
|
2020-03-27 22:44:16 -04:00 |
|
Blaise Tine
|
f3889f8744
|
missing simX changes from OPAE
|
2020-03-27 22:44:16 -04:00 |
|
Blaise Tine
|
e80fa7f233
|
missing rtl changes from OPAE
|
2020-03-27 22:37:35 -04:00 |
|