 Blaise Tine
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d0f2a3984d
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adding input buffering to bus arbiters to reduce backpressure delay propagation
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2020-12-05 17:31:29 -08:00 |
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Blaise Tine
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f3b1069ce8
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adding stream arbiter
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2020-12-03 06:40:23 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
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Blaise Tine
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bdfacf709c
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yosys synthesis refactoring
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2020-07-10 18:56:41 -04:00 |
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Blaise Tine
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75d66dc335
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fix sources.txt, run_ase.sh
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2020-06-29 12:52:28 -07:00 |
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felsabbagh3
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21566cdcd7
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Fixed Single Core with Optimizations
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2020-06-28 19:38:36 -07:00 |
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felsabbagh3
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ffb760cf73
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Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter
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2020-06-28 14:27:47 -07:00 |
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