+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
155 lines
4.0 KiB
C++
155 lines
4.0 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <iostream>
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#include <stdio.h>
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#include <stdlib.h>
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#include <cstdlib>
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#include <unistd.h>
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#include <assert.h>
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#include "fpga.h"
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#include "opae_sim.h"
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#include <VX_config.h>
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#include <util.h>
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using namespace vortex;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern fpga_result fpgaGetProperties(fpga_token token, fpga_properties *prop) {
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__unused (token, prop);
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return FPGA_OK;
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}
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extern fpga_result fpgaPropertiesSetObjectType(fpga_properties prop, fpga_objtype objtype) {
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__unused (prop, objtype);
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return FPGA_OK;
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}
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extern fpga_result fpgaPropertiesSetGUID(fpga_properties prop, fpga_guid guid) {
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__unused (prop, guid);
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return FPGA_OK;
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}
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extern fpga_result fpgaDestroyProperties(fpga_properties *prop) {
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__unused (prop);
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return FPGA_OK;
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}
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extern fpga_result fpgaEnumerate(const fpga_properties *filters, uint32_t num_filters, fpga_token *tokens, uint32_t max_tokens, uint32_t *num_matches) {
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__unused (filters, num_filters, num_filters, tokens, max_tokens);
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if (num_matches) {
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*num_matches = 1;
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}
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return FPGA_OK;
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}
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extern fpga_result fpgaDestroyToken(fpga_token *token) {
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__unused (token);
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return FPGA_OK;
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}
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extern fpga_result fpgaPropertiesGetLocalMemorySize(const fpga_properties *filters, uint64_t* lms) {
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__unused (filters);
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if (lms) {
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#if (XLEN == 64)
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*lms = 0x200000000; // 8 GB
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#else
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*lms = 0x100000000; // 4 GB
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#endif
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}
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return FPGA_OK;
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}
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extern fpga_result fpgaOpen(fpga_token token, fpga_handle *handle, int flags) {
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__unused (token);
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if (NULL == handle || flags != 0)
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return FPGA_INVALID_PARAM;
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auto sim = new opae_sim();
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*handle = reinterpret_cast<fpga_handle>(sim);
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return FPGA_OK;
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}
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extern fpga_result fpgaClose(fpga_handle handle) {
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if (NULL == handle)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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delete sim;
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return FPGA_OK;
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}
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extern fpga_result fpgaPrepareBuffer(fpga_handle handle, uint64_t len, void **buf_addr, uint64_t *wsid, int flags) {
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if (NULL == handle || len == 0 || buf_addr == NULL || wsid == NULL)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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int ret = sim->prepare_buffer(len, buf_addr, wsid, flags);
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if (ret != 0)
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return FPGA_NO_MEMORY;
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return FPGA_OK;
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}
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extern fpga_result fpgaReleaseBuffer(fpga_handle handle, uint64_t wsid) {
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if (NULL == handle)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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sim->release_buffer(wsid);
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return FPGA_OK;
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}
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extern fpga_result fpgaGetIOAddress(fpga_handle handle, uint64_t wsid, uint64_t *ioaddr) {
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if (NULL == handle || ioaddr == NULL)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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sim->get_io_address(wsid, ioaddr);
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return FPGA_OK;
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}
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extern fpga_result fpgaWriteMMIO64(fpga_handle handle, uint32_t mmio_num, uint64_t offset, uint64_t value) {
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if (NULL == handle || mmio_num != 0)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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sim->write_mmio64(mmio_num, offset, value);
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return FPGA_OK;
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}
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extern fpga_result fpgaReadMMIO64(fpga_handle handle, uint32_t mmio_num, uint64_t offset, uint64_t *value) {
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if (NULL == handle || mmio_num != 0 || value == NULL)
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return FPGA_INVALID_PARAM;
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auto sim = reinterpret_cast<opae_sim*>(handle);
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sim->read_mmio64(mmio_num, offset, value);
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return FPGA_OK;
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}
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extern const char *fpgaErrStr(fpga_result e) {
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return "";
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}
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#ifdef __cplusplus
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}
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#endif
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