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Tine, Blaise 0c886a8989 Update README.md
2020-01-11 10:40:26 -05:00
benchmarks
Vector evaluations
2019-11-25 22:18:12 -05:00
docs
update
2020-01-11 10:06:14 -05:00
emulator
VCD for power
2019-11-21 23:25:51 -05:00
models/memory
Added rf2_32x19_wm0 again
2019-11-11 14:28:45 -05:00
rtl
Fixed GPR Stage to be Generic when ASIC is defined
2019-11-22 09:20:20 -05:00
runtime
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2019-11-25 02:52:22 -05:00
rvvector
Merge remote-tracking branch 'refs/remotes/origin/master'
2019-11-24 09:00:43 -05:00
simX
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2019-11-25 02:52:22 -05:00
syn
Started synthesis script
2019-11-22 00:32:19 -05:00
.DS_Store
ram stdint + Quartus Files
2019-06-11 21:13:30 -07:00
.gitignore
migrated 100% to modelsim
2019-10-27 20:08:44 -04:00
README.md
Update README.md
2020-01-11 10:40:26 -05:00
results.txt
Less expensive but slower fetch logic
2019-05-05 22:55:47 -04:00
sftp-config.json
Started synthesis script
2019-11-22 00:32:19 -05:00
TODO
TODO update
2019-11-07 20:52:36 -05:00

README.md

Vortex RISC-V GPGPU

Vortex currently supported RISC-V RV32I ISA

/benchmarks containts test benchmarks

/docs contains documentation.

/runtime contains the runtime software support for Vortex.

/emulator contains a software emulator for Vortex.

/SimX contains a cycle-approximate simulator for Vortex.

/rtl is verilog for the processor. Currently supports RV32IM and passes all tests.

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Readme Apache-2.0 314 MiB
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