145 lines
3.9 KiB
Verilog
145 lines
3.9 KiB
Verilog
`include "VX_define.vh"
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module VX_fpu_unit #(
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parameter CORE_ID = 0
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) (
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// inputs
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input wire clk,
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input wire reset,
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// inputs
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VX_fpu_req_if fpu_req_if,
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VX_csr_to_fpu_if csr_to_fpu_if,
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// outputs
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VX_fpu_to_cmt_if fpu_commit_if
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);
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localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);
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wire ready_in;
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wire valid_out;
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wire ready_out;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire has_fflags;
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fflags_t [`NUM_THREADS-1:0] fflags;
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wire [`NUM_THREADS-1:0][31:0] result;
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wire [FPUQ_BITS-1:0] tag_in, tag_out;
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wire fpuq_full;
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wire fpuq_push = fpu_req_if.valid && fpu_req_if.ready;
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wire fpuq_pop = valid_out && ready_out;
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VX_cam_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1),
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.SIZE (`FPUQ_SIZE)
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) fpu_cam (
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.clk (clk),
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.reset (reset),
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.acquire_slot (fpuq_push),
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.write_addr (tag_in),
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.read_addr (tag_out),
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.release_addr (tag_out),
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.write_data ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}),
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.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}),
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.release_slot (fpuq_pop),
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.full (fpuq_full)
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);
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// can accept new request?
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assign fpu_req_if.ready = ready_in && ~fpuq_full;
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wire valid_in = fpu_req_if.valid && ~fpuq_full;
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// resolve dynamic FRM
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assign csr_to_fpu_if.wid = fpu_req_if.wid;
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wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.op_mod;
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`ifdef FPU_FAST
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VX_fp_fpga #(
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.TAGW (FPUQ_BITS)
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) fp_core (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.tag_in (tag_in),
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.op_type (fpu_req_if.op_type),
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.frm (fpu_frm),
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.dataa (fpu_req_if.rs1_data),
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.datab (fpu_req_if.rs2_data),
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.datac (fpu_req_if.rs3_data),
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.result (result),
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.has_fflags (has_fflags),
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.fflags (fflags),
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.tag_out (tag_out),
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.ready_out (ready_out),
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.valid_out (valid_out)
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);
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`else
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VX_fpnew #(
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.FMULADD (1),
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.FDIVSQRT (1),
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.FNONCOMP (1),
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.FCONV (1),
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.TAGW (FPUQ_BITS)
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) fp_core (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.tag_in (tag_in),
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.op_type (fpu_req_if.op_type),
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.frm (fpu_frm),
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.dataa (fpu_req_if.rs1_data),
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.datab (fpu_req_if.rs2_data),
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.datac (fpu_req_if.rs3_data),
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.result (result),
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.has_fflags (has_fflags),
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.fflags (fflags),
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.tag_out (tag_out),
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.ready_out (ready_out),
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.valid_out (valid_out)
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);
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`endif
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wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS))
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_out),
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.flush (1'b0),
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.in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}),
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.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags})
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);
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assign ready_out = ~stall_out;
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endmodule |