75 lines
1.6 KiB
Verilog
75 lines
1.6 KiB
Verilog
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module VX_register_file_slave (
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input wire clk,
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input wire in_warp,
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input wire in_wb_warp,
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input wire in_valid,
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input wire in_write_register,
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input wire[4:0] in_rd,
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input wire[31:0] in_data,
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input wire[4:0] in_src1,
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input wire[4:0] in_src2,
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input wire in_clone,
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input wire in_to_clone,
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input wire[31:0] in_regs[31:0],
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output reg[31:0] out_src1_data,
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output reg[31:0] out_src2_data
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);
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reg[31:0] registers[31:0];
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wire[31:0] write_data;
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wire[4:0] write_register;
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wire write_enable;
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// reg[5:0] i;
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// always @(posedge clk) begin
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// for (i = 0; i < 32; i++) begin
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// $display("%d: %h",i, registers[i[4:0]]);
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// end
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// end
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// integer i;
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// always @(*) begin
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// if (in_warp) begin
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// $display("TID: %d: %h",10,registers[10]);
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// $display("WID: %d: %h",11,registers[11]);
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// end
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// end
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assign write_data = in_data;
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assign write_register = in_rd;
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assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
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always @(posedge clk) begin
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if(write_enable && !in_clone) begin
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// $display("RF: Writing %h to %d",write_data, write_register);
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registers[write_register] <= write_data;
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end else if (in_clone && in_to_clone && in_warp) begin
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registers <= in_regs;
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end
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end
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// always @(posedge clk) begin
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// for (i = 0; i < 32; i = i + 1)
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// $display("(%d): %x", i, registers[i]);
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// end
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always @(negedge clk) begin
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out_src1_data <= registers[in_src1];
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out_src2_data <= registers[in_src2];
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end
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endmodule
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