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4c6a74fa8730c8cfc96758fa72ea75209862fed4
vortex/hw/rtl
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Blaise Tine 4c6a74fa87 cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
..
cache
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
fp_cores
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
2020-09-19 14:45:42 -04:00
interfaces
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
2020-09-19 14:45:42 -04:00
libs
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
cache refactoring - phase 2
2020-11-03 04:51:40 -08:00
VX_alu_unit.v
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
VX_cluster.v
minor fix
2020-11-03 15:34:35 -08:00
VX_commit.v
cache refactoring - phase 2
2020-11-03 04:51:40 -08:00
VX_config.vh
cache refactoring - phase 2
2020-11-03 04:51:40 -08:00
VX_core.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_csr_arb.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_csr_data.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_csr_io_arb.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_csr_unit.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_dcache_arb.v
pipeline refactoring
2020-07-19 05:03:47 -04:00
VX_decode.v
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
VX_define.vh
vlsim fix, verilator fst trace, use ram optimization
2020-10-25 16:40:50 -07:00
VX_execute.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_fetch.v
scope fixes
2020-10-13 08:44:55 -07:00
VX_fpu_unit.v
fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt
2020-09-08 07:05:26 -07:00
VX_gpr_bypass.v
minor update - 206-214 mhz
2020-08-29 05:14:08 -07:00
VX_gpr_ram.v
vlsim fix, verilator fst trace, use ram optimization
2020-10-25 16:40:50 -07:00
VX_gpr_stage.v
fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
2020-10-20 05:32:55 -07:00
VX_gpu_unit.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_ibuffer.v
fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
2020-10-20 05:32:55 -07:00
VX_icache_stage.v
basic test timing + scope tracing ccip
2020-10-27 17:04:04 -04:00
VX_instr_demux.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_io_arb.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_ipdom_stack.v
vlsim fix, verilator fst trace, use ram optimization
2020-10-25 16:40:50 -07:00
VX_issue.v
basic test timing + scope tracing ccip
2020-10-27 17:04:04 -04:00
VX_lsu_unit.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_mem_arb.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_mem_unit.v
cache refactoring - phase 2
2020-11-03 04:51:40 -08:00
VX_mul_unit.v
fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt
2020-09-08 07:05:26 -07:00
VX_pipeline.v
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_platform.vh
fixed afu to cpu mempcy hang
2020-10-28 14:19:13 -07:00
VX_print_instr.vh
optimize warp_sched
2020-08-24 05:36:00 -07:00
VX_scope.vh
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_scoreboard.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_types.vh
scope refactoring: adding modules definitions to VCD trace
2020-10-12 23:26:02 -04:00
VX_warp_sched.v
basic test timing + scope tracing ccip
2020-10-27 17:04:04 -04:00
VX_writeback.v
scope refactoring: adding modules definitions to VCD trace
2020-10-12 23:26:02 -04:00