480 lines
21 KiB
Verilog
480 lines
21 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache #(
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parameter CACHE_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 2048,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 4,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter CREQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 16,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 16,
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// Snoop Req Queue Size
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parameter SNRQ_SIZE = 16,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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// Enable snoop forwarding
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parameter SNOOP_FORWARDING = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 42,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 8,
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// dram request tag size
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parameter DRAM_TAG_WIDTH = 28,
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// Number of snoop forwarding requests
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parameter NUM_SNP_REQUESTS = 2,
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// Snooping request tag width
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parameter SNP_REQ_TAG_WIDTH = 28,
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// Snooping forward tag width
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parameter SNP_FWD_TAG_WIDTH = 1
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) (
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`SCOPE_SIGNALS_BANK_CACHE_IO
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] core_req_valid,
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input wire [`CORE_REQ_TAG_COUNT-1:0] core_req_rw,
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input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_ready,
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// Core response
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output wire [NUM_REQUESTS-1:0] core_rsp_valid,
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output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_ready,
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire snp_req_invalidate,
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input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// Snoop Forwarding out
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output wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_valid,
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output wire [NUM_SNP_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
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output wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_invalidate,
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output wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdout_tag,
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`IGNORE_WARNINGS_BEGIN
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input wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_ready,
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// Snoop forwarding in
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input wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_valid,
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input wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
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`IGNORE_WARNINGS_END
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output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
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);
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`ifdef DBG_CORE_REQ_INFO
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/* verilator lint_off UNUSED */
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wire[31:0] debug_core_req_use_pc;
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wire[`NR_BITS-1:0] debug_core_req_rd;
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wire[`NW_BITS-1:0] debug_core_req_wid;
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wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_core_req_idx;
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/* verilator lint_on UNUSED */
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if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
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assign {debug_core_req_use_pc, debug_core_req_rd, debug_core_req_wid, debug_core_req_idx} = core_req_tag[0];
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end
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`endif
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wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
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wire [NUM_BANKS-1:0] per_bank_core_req_ready;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr;
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wire dram_fill_req_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_req_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
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wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_wb_req_byteen;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr;
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wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data;
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wire [NUM_BANKS-1:0] per_bank_snp_req_ready;
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wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid;
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wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
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wire snp_req_valid_qual;
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wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr_qual;
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wire snp_req_invalidate_qual;
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wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag_qual;
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wire snp_req_ready_qual;
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if (SNOOP_FORWARDING) begin
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VX_snp_forwarder #(
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.CACHE_ID (CACHE_ID),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_REQUESTS (NUM_SNP_REQUESTS),
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.SNRQ_SIZE (SNRQ_SIZE),
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.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
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) snp_forwarder (
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.clk (clk),
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.reset (reset),
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.snp_req_valid (snp_req_valid),
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.snp_req_addr (snp_req_addr),
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.snp_req_invalidate (snp_req_invalidate),
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.snp_req_tag (snp_req_tag),
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.snp_req_ready (snp_req_ready),
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.snp_rsp_valid (snp_req_valid_qual),
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.snp_rsp_addr (snp_req_addr_qual),
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.snp_rsp_invalidate (snp_req_invalidate_qual),
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.snp_rsp_tag (snp_req_tag_qual),
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.snp_rsp_ready (snp_req_ready_qual),
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.snp_fwdout_valid (snp_fwdout_valid),
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.snp_fwdout_addr (snp_fwdout_addr),
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.snp_fwdout_invalidate(snp_fwdout_invalidate),
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.snp_fwdout_tag (snp_fwdout_tag),
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.snp_fwdout_ready (snp_fwdout_ready),
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.snp_fwdin_valid (snp_fwdin_valid),
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.snp_fwdin_tag (snp_fwdin_tag),
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.snp_fwdin_ready (snp_fwdin_ready)
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);
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end else begin
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assign snp_fwdout_valid = 0;
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assign snp_fwdout_addr = 0;
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assign snp_fwdout_invalidate = 0;
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assign snp_fwdout_tag = 0;
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assign snp_fwdin_ready = 0;
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assign snp_req_valid_qual = snp_req_valid;
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assign snp_req_addr_qual = snp_req_addr;
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assign snp_req_invalidate_qual = snp_req_invalidate;
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assign snp_req_tag_qual = snp_req_tag;
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assign snp_req_ready = snp_req_ready_qual;
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end
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if (NUM_BANKS == 1) begin
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assign snp_req_ready_qual = per_bank_snp_req_ready;
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end else begin
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assign snp_req_ready_qual = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr_qual)];
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end
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VX_cache_core_req_bank_sel #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS)
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) cache_core_req_bank_sel (
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.core_req_valid (core_req_valid),
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.per_bank_ready (per_bank_core_req_ready),
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.core_req_addr (core_req_addr),
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.per_bank_valid (per_bank_valid),
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.core_req_ready (core_req_ready)
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);
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assign dram_req_tag = dram_req_addr;
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assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready);
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid;
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wire [`CORE_REQ_TAG_COUNT-1:0] curr_bank_core_req_rw;
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wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
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wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
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wire curr_bank_core_rsp_valid;
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wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
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wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
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wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
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wire curr_bank_core_rsp_ready;
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wire curr_bank_dram_fill_rsp_valid;
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wire [`BANK_LINE_WIDTH-1:0] curr_bank_dram_fill_rsp_data;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr;
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wire curr_bank_dram_fill_rsp_ready;
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wire curr_bank_dram_fill_req_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_fill_req_ready;
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wire curr_bank_dram_wb_req_valid;
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wire [BANK_LINE_SIZE-1:0] curr_bank_dram_wb_req_byteen;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data;
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wire curr_bank_dram_wb_req_ready;
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wire curr_bank_snp_req_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
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wire curr_bank_snp_req_invalidate;
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wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_req_tag;
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wire curr_bank_snp_req_ready;
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wire curr_bank_snp_rsp_valid;
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wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
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wire curr_bank_snp_rsp_ready;
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wire curr_bank_core_req_ready;
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// Core Req
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assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}});
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assign curr_bank_core_req_addr = core_req_addr;
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assign curr_bank_core_req_rw = core_req_rw;
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assign curr_bank_core_req_byteen = core_req_byteen;
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assign curr_bank_core_req_data = core_req_data;
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assign curr_bank_core_req_tag = core_req_tag;
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assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
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// Core WB
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assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i];
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assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid;
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assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
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assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
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assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
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// Dram fill request
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assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid;
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if (NUM_BANKS == 1) begin
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assign per_bank_dram_fill_req_addr[i] = curr_bank_dram_fill_req_addr;
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end else begin
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assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i);
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end
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assign curr_bank_dram_fill_req_ready = dram_fill_req_ready;
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// Dram fill response
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if (NUM_BANKS == 1) begin
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assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid;
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assign curr_bank_dram_fill_rsp_addr = dram_rsp_tag;
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end else begin
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assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i);
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assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag);
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end
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assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
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assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready;
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// Dram writeback request
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assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
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assign per_bank_dram_wb_req_byteen[i] = curr_bank_dram_wb_req_byteen;
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if (NUM_BANKS == 1) begin
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assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr;
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end else begin
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assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
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end
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assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
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assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i];
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// Snoop request
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if (NUM_BANKS == 1) begin
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assign curr_bank_snp_req_valid = snp_req_valid_qual;
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assign curr_bank_snp_req_addr = snp_req_addr_qual;
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end else begin
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assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i);
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assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual);
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end
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assign curr_bank_snp_req_invalidate = snp_req_invalidate_qual;
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assign curr_bank_snp_req_tag = snp_req_tag_qual;
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assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready;
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// Snoop response
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assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid;
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assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag;
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assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i];
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VX_bank #(
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.BANK_ID (i),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.CREQ_SIZE (CREQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.DRAM_ENABLE (DRAM_ENABLE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.SNOOP_FORWARDING (SNOOP_FORWARDING),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
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.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
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) bank (
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`SCOPE_SIGNALS_BANK_SELECT(i)
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (curr_bank_core_req_valid),
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.core_req_rw (curr_bank_core_req_rw),
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.core_req_byteen (curr_bank_core_req_byteen),
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.core_req_addr (curr_bank_core_req_addr),
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.core_req_data (curr_bank_core_req_data),
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.core_req_tag (curr_bank_core_req_tag),
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.core_req_ready (curr_bank_core_req_ready),
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// Core response
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.core_rsp_valid (curr_bank_core_rsp_valid),
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.core_rsp_tid (curr_bank_core_rsp_tid),
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.core_rsp_data (curr_bank_core_rsp_data),
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.core_rsp_tag (curr_bank_core_rsp_tag),
|
|
.core_rsp_ready (curr_bank_core_rsp_ready),
|
|
|
|
// Dram fill request
|
|
.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
|
|
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
|
|
.dram_fill_req_ready (curr_bank_dram_fill_req_ready),
|
|
|
|
// Dram fill response
|
|
.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
|
|
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
|
|
.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
|
|
.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
|
|
|
|
// Dram writeback request
|
|
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
|
|
.dram_wb_req_byteen (curr_bank_dram_wb_req_byteen),
|
|
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
|
|
.dram_wb_req_data (curr_bank_dram_wb_req_data),
|
|
.dram_wb_req_ready (curr_bank_dram_wb_req_ready),
|
|
|
|
// Snoop request
|
|
.snp_req_valid (curr_bank_snp_req_valid),
|
|
.snp_req_addr (curr_bank_snp_req_addr),
|
|
.snp_req_invalidate (curr_bank_snp_req_invalidate),
|
|
.snp_req_tag (curr_bank_snp_req_tag),
|
|
.snp_req_ready (curr_bank_snp_req_ready),
|
|
|
|
// Snoop response
|
|
.snp_rsp_valid (curr_bank_snp_rsp_valid),
|
|
.snp_rsp_tag (curr_bank_snp_rsp_tag),
|
|
.snp_rsp_ready (curr_bank_snp_rsp_ready)
|
|
);
|
|
end
|
|
|
|
VX_cache_dram_req_arb #(
|
|
.BANK_LINE_SIZE (BANK_LINE_SIZE),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE (WORD_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE)
|
|
) cache_dram_req_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid),
|
|
.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
|
|
.dram_fill_req_ready (dram_fill_req_ready),
|
|
.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
|
|
.per_bank_dram_wb_req_byteen (per_bank_dram_wb_req_byteen),
|
|
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
|
|
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
|
|
.per_bank_dram_wb_req_ready (per_bank_dram_wb_req_ready),
|
|
.dram_req_valid (dram_req_valid),
|
|
.dram_req_rw (dram_req_rw),
|
|
.dram_req_byteen (dram_req_byteen),
|
|
.dram_req_addr (dram_req_addr),
|
|
.dram_req_data (dram_req_data),
|
|
.dram_req_ready (dram_req_ready)
|
|
);
|
|
|
|
VX_cache_core_rsp_merge #(
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE (WORD_SIZE),
|
|
.NUM_REQUESTS (NUM_REQUESTS),
|
|
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
|
|
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
|
|
) cache_core_rsp_merge (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
|
|
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
|
|
.per_bank_core_rsp_data (per_bank_core_rsp_data),
|
|
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
|
|
.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
|
|
.core_rsp_valid (core_rsp_valid),
|
|
.core_rsp_data (core_rsp_data),
|
|
.core_rsp_tag (core_rsp_tag),
|
|
.core_rsp_ready (core_rsp_ready)
|
|
);
|
|
|
|
VX_snp_rsp_arb #(
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.BANK_LINE_SIZE (BANK_LINE_SIZE),
|
|
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
|
|
) snp_rsp_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.per_bank_snp_rsp_valid (per_bank_snp_rsp_valid),
|
|
.per_bank_snp_rsp_tag (per_bank_snp_rsp_tag),
|
|
.per_bank_snp_rsp_ready (per_bank_snp_rsp_ready),
|
|
.snp_rsp_valid (snp_rsp_valid),
|
|
.snp_rsp_tag (snp_rsp_tag),
|
|
.snp_rsp_ready (snp_rsp_ready)
|
|
);
|
|
|
|
endmodule
|