111 lines
2.7 KiB
Verilog
111 lines
2.7 KiB
Verilog
`include "VX_define.v"
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module VX_front_end (
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input wire clk,
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input wire reset,
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input wire forwarding_fwd_stall,
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input wire memory_delay,
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input wire execute_branch_stall,
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VX_icache_response_inter icache_response_fe,
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VX_icache_request_inter icache_request_fe,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_wb_inter VX_writeback_inter,
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VX_forward_reqeust_inter VX_fwd_req_de,
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VX_forward_response_inter VX_fwd_rsp,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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output wire[11:0] decode_csr_address,
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output wire fetch_delay,
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output wire fetch_ebreak
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);
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wire[`NW_M1:0] fetch_which_warp;
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VX_warp_ctl_inter VX_warp_ctl();
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VX_inst_meta_inter fe_inst_meta_fd();
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VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
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VX_inst_meta_inter fd_inst_meta_de();
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// From decode
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wire decode_branch_stall;
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wire decode_clone_stall;
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wire total_freeze = memory_delay || fetch_delay;
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VX_fetch vx_fetch(
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.clk (clk),
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.reset (reset),
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.in_memory_delay (memory_delay),
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.in_branch_stall (decode_branch_stall),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_branch_stall_exe(execute_branch_stall),
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.in_clone_stall (decode_clone_stall),
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.VX_jal_rsp (VX_jal_rsp),
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.icache_response (icache_response_fe),
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.VX_warp_ctl (VX_warp_ctl),
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.icache_request (icache_request_fe),
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.VX_branch_rsp (VX_branch_rsp),
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.out_delay (fetch_delay),
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.out_ebreak (fetch_ebreak),
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.out_which_wspawn (fetch_which_warp),
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.fe_inst_meta_fd (fe_inst_meta_fd)
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);
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VX_f_d_reg vx_f_d_reg(
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.clk (clk),
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.reset (reset),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_freeze (total_freeze),
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.in_clone_stall (decode_clone_stall),
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.fe_inst_meta_fd(fe_inst_meta_fd),
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.fd_inst_meta_de(fd_inst_meta_de)
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);
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VX_decode vx_decode(
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.clk (clk),
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.fd_inst_meta_de (fd_inst_meta_de),
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.VX_writeback_inter(VX_writeback_inter),
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.VX_fwd_rsp (VX_fwd_rsp),
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.in_which_wspawn (fetch_which_warp),
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.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
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.VX_fwd_req_de (VX_fwd_req_de),
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.VX_warp_ctl (VX_warp_ctl),
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.out_clone_stall (decode_clone_stall),
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.out_branch_stall (decode_branch_stall)
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);
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VX_d_e_reg vx_d_e_reg(
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.clk (clk),
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.reset (reset),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_branch_stall(execute_branch_stall),
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.in_freeze (total_freeze),
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.in_clone_stall (decode_clone_stall),
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.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
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.VX_bckE_req (VX_bckE_req)
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);
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assign decode_csr_address = VX_frE_to_bckE_req.csr_address;
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endmodule
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