42 lines
1.1 KiB
Verilog
42 lines
1.1 KiB
Verilog
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`include "VX_define.v"
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module VX_gpr (
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input wire clk,
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input wire valid_write_request,
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input wire valid_read_request,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data
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);
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logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
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wire write_enable;
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assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// assign read_enable = valid_request;
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genvar thread_index;
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always_ff@(posedge clk)
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begin
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if (write_enable) begin
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for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
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if (VX_writeback_inter.wb_valid[thread_index]) begin
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gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
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end
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end
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end
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end
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always @(negedge clk) begin
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if (valid_read_request) begin
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out_a_reg_data <= gpr[VX_gpr_read.rs1];
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out_b_reg_data <= gpr[VX_gpr_read.rs2];
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end
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end
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endmodule |