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New GPR structure - Clone or WSPAWN

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This commit is contained in:
felsabbagh3
2019-09-09 22:17:20 -04:00
parent 1882147370
commit 4e8da1811a
21 changed files with 1997 additions and 6204 deletions
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485
kernel/vortex_test.dump
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@@ -75,7 +75,7 @@ Disassembly of section .text:
800000d4 <vx_save_context>:
800000d4: 01000217 auipc tp,0x1000
800000d8: 25820213 addi tp,tp,600 # 8100032c <context>
800000d8: 23c20213 addi tp,tp,572 # 81000310 <context>
800000dc: 00022023 sw zero,0(tp) # 0 <A_WARPS-0x7>
800000e0: 00122223 sw ra,4(tp) # 4 <A_WARPS-0x3>
800000e4: 00222423 sw sp,8(tp) # 8 <A_WARPS+0x1>
@@ -113,7 +113,7 @@ Disassembly of section .text:
80000164 <vx_load_context>:
80000164: 01000217 auipc tp,0x1000
80000168: 1c820213 addi tp,tp,456 # 8100032c <context>
80000168: 1ac20213 addi tp,tp,428 # 81000310 <context>
8000016c: 00022003 lw zero,0(tp) # 0 <A_WARPS-0x7>
80000170: 00422083 lw ra,4(tp) # 4 <A_WARPS-0x3>
80000174: 00822103 lw sp,8(tp) # 8 <A_WARPS+0x1>
@@ -169,7 +169,7 @@ Disassembly of section .text:
80000224: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
80000228: 02f70733 mul a4,a4,a5
8000022c: 810007b7 lui a5,0x81000
80000230: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
80000230: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
80000234: 00f707b3 add a5,a4,a5
80000238: 00078513 mv a0,a5
8000023c: 440000ef jal ra,8000067c <queue_initialize>
@@ -197,7 +197,7 @@ Disassembly of section .text:
8000028c: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
80000290: 02f70733 mul a4,a4,a5
80000294: 810007b7 lui a5,0x81000
80000298: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
80000298: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
8000029c: 00f707b3 add a5,a4,a5
800002a0: 00078513 mv a0,a5
800002a4: 504000ef jal ra,800007a8 <queue_isEmpty>
@@ -206,7 +206,7 @@ Disassembly of section .text:
800002b0: 000d0713 mv a4,s10
800002b4: 810007b7 lui a5,0x81000
800002b8: 00271713 slli a4,a4,0x2
800002bc: 28478793 addi a5,a5,644 # 81000284 <barrier_bool+0xfffd6fa4>
800002bc: 26878793 addi a5,a5,616 # 81000268 <barrier_bool+0xfffd6fa4>
800002c0: 00f707b3 add a5,a4,a5
800002c4: 00100713 li a4,1
800002c8: 00e7a023 sw a4,0(a5)
@@ -220,7 +220,7 @@ Disassembly of section .text:
800002e8: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
800002ec: 02f70733 mul a4,a4,a5
800002f0: 810007b7 lui a5,0x81000
800002f4: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
800002f4: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
800002f8: 00f707b3 add a5,a4,a5
800002fc: fd840713 addi a4,s0,-40
80000300: 00070593 mv a1,a4
@@ -258,7 +258,7 @@ Disassembly of section .text:
80000378: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
8000037c: 02f70733 mul a4,a4,a5
80000380: 810007b7 lui a5,0x81000
80000384: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
80000384: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
80000388: 00f707b3 add a5,a4,a5
8000038c: 00078513 mv a0,a5
80000390: 418000ef jal ra,800007a8 <queue_isEmpty>
@@ -269,7 +269,7 @@ Disassembly of section .text:
800003a4: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
800003a8: 02f70733 mul a4,a4,a5
800003ac: 810007b7 lui a5,0x81000
800003b0: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
800003b0: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
800003b4: 00f707b3 add a5,a4,a5
800003b8: fd040713 addi a4,s0,-48
800003bc: 00070593 mv a1,a4
@@ -295,14 +295,14 @@ Disassembly of section .text:
8000040c: 00020793 mv a5,tp
80000410: 04078863 beqz a5,80000460 <vx_schedule_warps+0x118>
80000414: 810007b7 lui a5,0x81000
80000418: 42c78513 addi a0,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
80000418: 41078513 addi a0,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
8000041c: 38c000ef jal ra,800007a8 <queue_isEmpty>
80000420: 00050793 mv a5,a0
80000424: 02079e63 bnez a5,80000460 <vx_schedule_warps+0x118>
80000428: fb840793 addi a5,s0,-72
8000042c: 00078593 mv a1,a5
80000430: 810007b7 lui a5,0x81000
80000434: 42c78513 addi a0,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
80000434: 41078513 addi a0,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
80000438: 2d0000ef jal ra,80000708 <queue_dequeue>
8000043c: fc042783 lw a5,-64(s0)
80000440: 00078113 mv sp,a5
@@ -354,7 +354,7 @@ Disassembly of section .text:
800004f0: 97478793 addi a5,a5,-1676 # 974 <SIZE+0x942>
800004f4: 02f70733 mul a4,a4,a5
800004f8: 810007b7 lui a5,0x81000
800004fc: 42c78793 addi a5,a5,1068 # 8100042c <barrier_bool+0xfffd714c>
800004fc: 41078793 addi a5,a5,1040 # 81000410 <barrier_bool+0xfffd714c>
80000500: 00f707b3 add a5,a4,a5
80000504: fcc40713 addi a4,s0,-52
80000508: 00070593 mv a1,a4
@@ -389,7 +389,7 @@ Disassembly of section .text:
80000574: fca42e23 sw a0,-36(s0)
80000578: fdc42583 lw a1,-36(s0)
8000057c: 810007b7 lui a5,0x81000
80000580: 04078513 addi a0,a5,64 # 81000040 <barrier_bool+0xfffd6d60>
80000580: 04078513 addi a0,a5,64 # 81000040 <barrier_bool+0xfffd6d7c>
80000584: 354000ef jal ra,800008d8 <vx_printf>
80000588: c6dff0ef jal ra,800001f4 <vx_available_warps>
8000058c: fea42023 sw a0,-32(s0)
@@ -402,7 +402,7 @@ Disassembly of section .text:
800005a8: 810007b7 lui a5,0x81000
800005ac: fe842703 lw a4,-24(s0)
800005b0: 00271713 slli a4,a4,0x2
800005b4: 28478793 addi a5,a5,644 # 81000284 <barrier_bool+0xfffd6fa4>
800005b4: 26878793 addi a5,a5,616 # 81000268 <barrier_bool+0xfffd6fa4>
800005b8: 00f707b3 add a5,a4,a5
800005bc: 0007a703 lw a4,0(a5)
800005c0: 00100793 li a5,1
@@ -418,7 +418,7 @@ Disassembly of section .text:
800005e8: fce7d0e3 bge a5,a4,800005a8 <vx_wait_for_warps+0x44>
800005ec: fec42583 lw a1,-20(s0)
800005f0: 810007b7 lui a5,0x81000
800005f4: 04c78513 addi a0,a5,76 # 8100004c <barrier_bool+0xfffd6d6c>
800005f4: 04c78513 addi a0,a5,76 # 8100004c <barrier_bool+0xfffd6d88>
800005f8: 2e0000ef jal ra,800008d8 <vx_printf>
800005fc: fec42703 lw a4,-20(s0)
80000600: fdc42783 lw a5,-36(s0)
@@ -428,7 +428,7 @@ Disassembly of section .text:
80000610: 810007b7 lui a5,0x81000
80000614: fe442703 lw a4,-28(s0)
80000618: 00271713 slli a4,a4,0x2
8000061c: 28478793 addi a5,a5,644 # 81000284 <barrier_bool+0xfffd6fa4>
8000061c: 26878793 addi a5,a5,616 # 81000268 <barrier_bool+0xfffd6fa4>
80000620: 00f707b3 add a5,a4,a5
80000624: 0007a023 sw zero,0(a5)
80000628: fe442783 lw a5,-28(s0)
@@ -597,7 +597,7 @@ Disassembly of section .text:
80000834: 810007b7 lui a5,0x81000
80000838: fdc42703 lw a4,-36(s0)
8000083c: 00271713 slli a4,a4,0x2
80000840: 1c478793 addi a5,a5,452 # 810001c4 <barrier_bool+0xfffd6ee4>
80000840: 1a878793 addi a5,a5,424 # 810001a8 <barrier_bool+0xfffd6ee4>
80000844: 00f707b3 add a5,a4,a5
80000848: 0007a783 lw a5,0(a5)
8000084c: 00078513 mv a0,a5
@@ -621,7 +621,7 @@ Disassembly of section .text:
80000894: 810007b7 lui a5,0x81000
80000898: fe442703 lw a4,-28(s0)
8000089c: 00271713 slli a4,a4,0x2
800008a0: 1c478793 addi a5,a5,452 # 810001c4 <barrier_bool+0xfffd6ee4>
800008a0: 1a878793 addi a5,a5,424 # 810001a8 <barrier_bool+0xfffd6ee4>
800008a4: 00f707b3 add a5,a4,a5
800008a8: 0007a783 lw a5,0(a5)
800008ac: 00078513 mv a0,a5
@@ -648,7 +648,7 @@ Disassembly of section .text:
800008f8: fe842503 lw a0,-24(s0)
800008fc: f19ff0ef jal ra,80000814 <vx_print_hex>
80000900: 810007b7 lui a5,0x81000
80000904: 09478513 addi a0,a5,148 # 81000094 <barrier_bool+0xfffd6db4>
80000904: 09478513 addi a0,a5,148 # 81000094 <barrier_bool+0xfffd6dd0>
80000908: ed1ff0ef jal ra,800007d8 <vx_print_str>
8000090c: 00000013 nop
80000910: 01c12083 lw ra,28(sp)
@@ -667,17 +667,17 @@ Disassembly of section .text:
8000093c: fcd42823 sw a3,-48(s0)
80000940: 810267b7 lui a5,0x81026
80000944: fdc42703 lw a4,-36(s0)
80000948: 1ce7aa23 sw a4,468(a5) # 810261d4 <barrier_bool+0xffffcef4>
80000948: 1ae7ac23 sw a4,440(a5) # 810261b8 <barrier_bool+0xffffcef4>
8000094c: 810267b7 lui a5,0x81026
80000950: 1d478793 addi a5,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
80000950: 1b878793 addi a5,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
80000954: fd842703 lw a4,-40(s0)
80000958: 00e7a223 sw a4,4(a5)
8000095c: 810267b7 lui a5,0x81026
80000960: 1d478793 addi a5,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
80000960: 1b878793 addi a5,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
80000964: fd442703 lw a4,-44(s0)
80000968: 00e7a423 sw a4,8(a5)
8000096c: 810267b7 lui a5,0x81026
80000970: 1d478793 addi a5,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
80000970: 1b878793 addi a5,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
80000974: fd042703 lw a4,-48(s0)
80000978: 00e7a623 sw a4,12(a5)
8000097c: 881ff0ef jal ra,800001fc <vx_available_threads>
@@ -694,24 +694,24 @@ Disassembly of section .text:
800009a8: 00178793 addi a5,a5,1
800009ac: fef42623 sw a5,-20(s0)
800009b0: 810267b7 lui a5,0x81026
800009b4: 1d478793 addi a5,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
800009b4: 1b878793 addi a5,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
800009b8: fec42703 lw a4,-20(s0)
800009bc: 00e7a823 sw a4,16(a5)
800009c0: fd042703 lw a4,-48(s0)
800009c4: fe842783 lw a5,-24(s0)
800009c8: 02f76263 bltu a4,a5,800009ec <vx_sq_mat_mult+0xcc>
800009cc: 810267b7 lui a5,0x81026
800009d0: 1d478693 addi a3,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
800009d0: 1b878693 addi a3,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
800009d4: 800017b7 lui a5,0x80001
800009d8: a4478613 addi a2,a5,-1468 # 80000a44 <barrier_bool+0xfefd7764>
800009d8: a4478613 addi a2,a5,-1468 # 80000a44 <barrier_bool+0xfefd7780>
800009dc: fe842583 lw a1,-24(s0)
800009e0: fd042503 lw a0,-48(s0)
800009e4: a91ff0ef jal ra,80000474 <vx_spawnWarps>
800009e8: 0200006f j 80000a08 <vx_sq_mat_mult+0xe8>
800009ec: 810267b7 lui a5,0x81026
800009f0: 1d478693 addi a3,a5,468 # 810261d4 <barrier_bool+0xffffcef4>
800009f0: 1b878693 addi a3,a5,440 # 810261b8 <barrier_bool+0xffffcef4>
800009f4: 800017b7 lui a5,0x80001
800009f8: a4478613 addi a2,a5,-1468 # 80000a44 <barrier_bool+0xfefd7764>
800009f8: a4478613 addi a2,a5,-1468 # 80000a44 <barrier_bool+0xfefd7780>
800009fc: fd042583 lw a1,-48(s0)
80000a00: fd042503 lw a0,-48(s0)
80000a04: a71ff0ef jal ra,80000474 <vx_spawnWarps>
@@ -841,21 +841,21 @@ Disassembly of section .text:
80000be4: fce42623 sw a4,-52(s0)
80000be8: 810267b7 lui a5,0x81026
80000bec: fdc42703 lw a4,-36(s0)
80000bf0: 1ee7a423 sw a4,488(a5) # 810261e8 <barrier_bool+0xffffcf08>
80000bf0: 1ce7a623 sw a4,460(a5) # 810261cc <barrier_bool+0xffffcf08>
80000bf4: 810267b7 lui a5,0x81026
80000bf8: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000bf8: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000bfc: fd842703 lw a4,-40(s0)
80000c00: 00e7a223 sw a4,4(a5)
80000c04: 810267b7 lui a5,0x81026
80000c08: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000c08: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000c0c: fd442703 lw a4,-44(s0)
80000c10: 00e7a423 sw a4,8(a5)
80000c14: 810267b7 lui a5,0x81026
80000c18: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000c18: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000c1c: fcc42703 lw a4,-52(s0)
80000c20: 00e7a623 sw a4,12(a5)
80000c24: 810267b7 lui a5,0x81026
80000c28: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000c28: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000c2c: fd042703 lw a4,-48(s0)
80000c30: 00e7a823 sw a4,16(a5)
80000c34: dc8ff0ef jal ra,800001fc <vx_available_threads>
@@ -872,24 +872,24 @@ Disassembly of section .text:
80000c60: 00178793 addi a5,a5,1
80000c64: fef42623 sw a5,-20(s0)
80000c68: 810267b7 lui a5,0x81026
80000c6c: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000c6c: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000c70: fec42703 lw a4,-20(s0)
80000c74: 00e7aa23 sw a4,20(a5)
80000c78: fcc42703 lw a4,-52(s0)
80000c7c: fe842783 lw a5,-24(s0)
80000c80: 02f76263 bltu a4,a5,80000ca4 <vx_mat_add+0xe0>
80000c84: 810267b7 lui a5,0x81026
80000c88: 1e878693 addi a3,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000c88: 1cc78693 addi a3,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000c8c: 800017b7 lui a5,0x80001
80000c90: cfc78613 addi a2,a5,-772 # 80000cfc <barrier_bool+0xfefd7a1c>
80000c90: cfc78613 addi a2,a5,-772 # 80000cfc <barrier_bool+0xfefd7a38>
80000c94: fe842583 lw a1,-24(s0)
80000c98: fd042503 lw a0,-48(s0)
80000c9c: fd8ff0ef jal ra,80000474 <vx_spawnWarps>
80000ca0: 0200006f j 80000cc0 <vx_mat_add+0xfc>
80000ca4: 810267b7 lui a5,0x81026
80000ca8: 1e878693 addi a3,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000ca8: 1cc78693 addi a3,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000cac: 800017b7 lui a5,0x80001
80000cb0: cfc78613 addi a2,a5,-772 # 80000cfc <barrier_bool+0xfefd7a1c>
80000cb0: cfc78613 addi a2,a5,-772 # 80000cfc <barrier_bool+0xfefd7a38>
80000cb4: fcc42583 lw a1,-52(s0)
80000cb8: fd042503 lw a0,-48(s0)
80000cbc: fb8ff0ef jal ra,80000474 <vx_spawnWarps>
@@ -962,7 +962,7 @@ Disassembly of section .text:
80000dc0: fc744783 lbu a5,-57(s0)
80000dc4: 00078f13 mv t5,a5
80000dc8: 800017b7 lui a5,0x80001
80000dcc: e3078f93 addi t6,a5,-464 # 80000e30 <barrier_bool+0xfefd7b50>
80000dcc: e3078f93 addi t6,a5,-464 # 80000e30 <barrier_bool+0xfefd7b6c>
80000dd0: 000f206b 0xf206b
80000dd4: 01ff707b 0x1ff707b
80000dd8: fcc42783 lw a5,-52(s0)
@@ -985,7 +985,7 @@ Disassembly of section .text:
80000e1c: 00178793 addi a5,a5,1
80000e20: fef42423 sw a5,-24(s0)
80000e24: 800017b7 lui a5,0x80001
80000e28: e3478e13 addi t3,a5,-460 # 80000e34 <barrier_bool+0xfefd7b54>
80000e28: e3478e13 addi t3,a5,-460 # 80000e34 <barrier_bool+0xfefd7b70>
80000e2c: 000e0067 jr t3
80000e30: 00000013 nop
80000e34: 0000306b 0x306b
@@ -1013,21 +1013,21 @@ Disassembly of section .text:
80000e84: fce42623 sw a4,-52(s0)
80000e88: 810267b7 lui a5,0x81026
80000e8c: fdc42703 lw a4,-36(s0)
80000e90: 1ee7a423 sw a4,488(a5) # 810261e8 <barrier_bool+0xffffcf08>
80000e90: 1ce7a623 sw a4,460(a5) # 810261cc <barrier_bool+0xffffcf08>
80000e94: 810267b7 lui a5,0x81026
80000e98: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000e98: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000e9c: fd842703 lw a4,-40(s0)
80000ea0: 00e7a223 sw a4,4(a5)
80000ea4: 810267b7 lui a5,0x81026
80000ea8: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000ea8: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000eac: fd442703 lw a4,-44(s0)
80000eb0: 00e7a423 sw a4,8(a5)
80000eb4: 810267b7 lui a5,0x81026
80000eb8: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000eb8: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000ebc: fcc42703 lw a4,-52(s0)
80000ec0: 00e7a623 sw a4,12(a5)
80000ec4: 810267b7 lui a5,0x81026
80000ec8: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000ec8: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000ecc: fd042703 lw a4,-48(s0)
80000ed0: 00e7a823 sw a4,16(a5)
80000ed4: b28ff0ef jal ra,800001fc <vx_available_threads>
@@ -1044,24 +1044,24 @@ Disassembly of section .text:
80000f00: 00178793 addi a5,a5,1
80000f04: fef42623 sw a5,-20(s0)
80000f08: 810267b7 lui a5,0x81026
80000f0c: 1e878793 addi a5,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000f0c: 1cc78793 addi a5,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000f10: fec42703 lw a4,-20(s0)
80000f14: 00e7aa23 sw a4,20(a5)
80000f18: fcc42703 lw a4,-52(s0)
80000f1c: fe842783 lw a5,-24(s0)
80000f20: 02f76263 bltu a4,a5,80000f44 <vx_mat_sub+0xe0>
80000f24: 810267b7 lui a5,0x81026
80000f28: 1e878693 addi a3,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000f28: 1cc78693 addi a3,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000f2c: 800017b7 lui a5,0x80001
80000f30: f9c78613 addi a2,a5,-100 # 80000f9c <barrier_bool+0xfefd7cbc>
80000f30: f9c78613 addi a2,a5,-100 # 80000f9c <barrier_bool+0xfefd7cd8>
80000f34: fe842583 lw a1,-24(s0)
80000f38: fd042503 lw a0,-48(s0)
80000f3c: d38ff0ef jal ra,80000474 <vx_spawnWarps>
80000f40: 0200006f j 80000f60 <vx_mat_sub+0xfc>
80000f44: 810267b7 lui a5,0x81026
80000f48: 1e878693 addi a3,a5,488 # 810261e8 <barrier_bool+0xffffcf08>
80000f48: 1cc78693 addi a3,a5,460 # 810261cc <barrier_bool+0xffffcf08>
80000f4c: 800017b7 lui a5,0x80001
80000f50: f9c78613 addi a2,a5,-100 # 80000f9c <barrier_bool+0xfefd7cbc>
80000f50: f9c78613 addi a2,a5,-100 # 80000f9c <barrier_bool+0xfefd7cd8>
80000f54: fcc42583 lw a1,-52(s0)
80000f58: fd042503 lw a0,-48(s0)
80000f5c: d18ff0ef jal ra,80000474 <vx_spawnWarps>
@@ -1134,7 +1134,7 @@ Disassembly of section .text:
80001060: fc744783 lbu a5,-57(s0)
80001064: 00078f13 mv t5,a5
80001068: 800017b7 lui a5,0x80001
8000106c: 0d078f93 addi t6,a5,208 # 800010d0 <barrier_bool+0xfefd7df0>
8000106c: 0d078f93 addi t6,a5,208 # 800010d0 <barrier_bool+0xfefd7e0c>
80001070: 000f206b 0xf206b
80001074: 01ff707b 0x1ff707b
80001078: fcc42783 lw a5,-52(s0)
@@ -1157,7 +1157,7 @@ Disassembly of section .text:
800010bc: 00178793 addi a5,a5,1
800010c0: fef42423 sw a5,-24(s0)
800010c4: 800017b7 lui a5,0x80001
800010c8: 0d478e13 addi t3,a5,212 # 800010d4 <barrier_bool+0xfefd7df4>
800010c8: 0d478e13 addi t3,a5,212 # 800010d4 <barrier_bool+0xfefd7e10>
800010cc: 000e0067 jr t3
800010d0: 00000013 nop
800010d4: 0000306b 0x306b
@@ -1185,21 +1185,21 @@ Disassembly of section .text:
80001124: fce42623 sw a4,-52(s0)
80001128: 810267b7 lui a5,0x81026
8000112c: fdc42703 lw a4,-36(s0)
80001130: 20e7a023 sw a4,512(a5) # 81026200 <barrier_bool+0xffffcf20>
80001130: 1ee7a223 sw a4,484(a5) # 810261e4 <barrier_bool+0xffffcf20>
80001134: 810267b7 lui a5,0x81026
80001138: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
80001138: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
8000113c: fd842703 lw a4,-40(s0)
80001140: 00e7a223 sw a4,4(a5)
80001144: 810267b7 lui a5,0x81026
80001148: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
80001148: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
8000114c: fd442703 lw a4,-44(s0)
80001150: 00e7a423 sw a4,8(a5)
80001154: 810267b7 lui a5,0x81026
80001158: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
80001158: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
8000115c: fcc42703 lw a4,-52(s0)
80001160: 00e7a623 sw a4,12(a5)
80001164: 810267b7 lui a5,0x81026
80001168: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
80001168: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
8000116c: fd042703 lw a4,-48(s0)
80001170: 00e7a823 sw a4,16(a5)
80001174: 888ff0ef jal ra,800001fc <vx_available_threads>
@@ -1216,24 +1216,24 @@ Disassembly of section .text:
800011a0: 00178793 addi a5,a5,1
800011a4: fef42623 sw a5,-20(s0)
800011a8: 810267b7 lui a5,0x81026
800011ac: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800011ac: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800011b0: fec42703 lw a4,-20(s0)
800011b4: 00e7aa23 sw a4,20(a5)
800011b8: fcc42703 lw a4,-52(s0)
800011bc: fe842783 lw a5,-24(s0)
800011c0: 02f76263 bltu a4,a5,800011e4 <vx_e_mat_add+0xe0>
800011c4: 810267b7 lui a5,0x81026
800011c8: 20078693 addi a3,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800011c8: 1e478693 addi a3,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800011cc: 800017b7 lui a5,0x80001
800011d0: 23c78613 addi a2,a5,572 # 8000123c <barrier_bool+0xfefd7f5c>
800011d0: 23c78613 addi a2,a5,572 # 8000123c <barrier_bool+0xfefd7f78>
800011d4: fe842583 lw a1,-24(s0)
800011d8: fd042503 lw a0,-48(s0)
800011dc: a98ff0ef jal ra,80000474 <vx_spawnWarps>
800011e0: 0200006f j 80001200 <vx_e_mat_add+0xfc>
800011e4: 810267b7 lui a5,0x81026
800011e8: 20078693 addi a3,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800011e8: 1e478693 addi a3,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800011ec: 800017b7 lui a5,0x80001
800011f0: 23c78613 addi a2,a5,572 # 8000123c <barrier_bool+0xfefd7f5c>
800011f0: 23c78613 addi a2,a5,572 # 8000123c <barrier_bool+0xfefd7f78>
800011f4: fcc42583 lw a1,-52(s0)
800011f8: fd042503 lw a0,-48(s0)
800011fc: a78ff0ef jal ra,80000474 <vx_spawnWarps>
@@ -1307,7 +1307,7 @@ Disassembly of section .text:
80001304: fc744783 lbu a5,-57(s0)
80001308: 00078f13 mv t5,a5
8000130c: 800017b7 lui a5,0x80001
80001310: 36478f93 addi t6,a5,868 # 80001364 <barrier_bool+0xfefd8084>
80001310: 36478f93 addi t6,a5,868 # 80001364 <barrier_bool+0xfefd80a0>
80001314: 000f206b 0xf206b
80001318: 01ff707b 0x1ff707b
8000131c: fcc42783 lw a5,-52(s0)
@@ -1326,7 +1326,7 @@ Disassembly of section .text:
80001350: 00178793 addi a5,a5,1
80001354: fef42423 sw a5,-24(s0)
80001358: 800017b7 lui a5,0x80001
8000135c: 36878e13 addi t3,a5,872 # 80001368 <barrier_bool+0xfefd8088>
8000135c: 36878e13 addi t3,a5,872 # 80001368 <barrier_bool+0xfefd80a4>
80001360: 000e0067 jr t3
80001364: 00000013 nop
80001368: 0000306b 0x306b
@@ -1354,21 +1354,21 @@ Disassembly of section .text:
800013b8: fce42623 sw a4,-52(s0)
800013bc: 810267b7 lui a5,0x81026
800013c0: fdc42703 lw a4,-36(s0)
800013c4: 20e7a023 sw a4,512(a5) # 81026200 <barrier_bool+0xffffcf20>
800013c4: 1ee7a223 sw a4,484(a5) # 810261e4 <barrier_bool+0xffffcf20>
800013c8: 810267b7 lui a5,0x81026
800013cc: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800013cc: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800013d0: fd842703 lw a4,-40(s0)
800013d4: 00e7a223 sw a4,4(a5)
800013d8: 810267b7 lui a5,0x81026
800013dc: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800013dc: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800013e0: fd442703 lw a4,-44(s0)
800013e4: 00e7a423 sw a4,8(a5)
800013e8: 810267b7 lui a5,0x81026
800013ec: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800013ec: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
800013f0: fcc42703 lw a4,-52(s0)
800013f4: 00e7a623 sw a4,12(a5)
800013f8: 810267b7 lui a5,0x81026
800013fc: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
800013fc: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
80001400: fd042703 lw a4,-48(s0)
80001404: 00e7a823 sw a4,16(a5)
80001408: df5fe0ef jal ra,800001fc <vx_available_threads>
@@ -1385,24 +1385,24 @@ Disassembly of section .text:
80001434: 00178793 addi a5,a5,1
80001438: fef42623 sw a5,-20(s0)
8000143c: 810267b7 lui a5,0x81026
80001440: 20078793 addi a5,a5,512 # 81026200 <barrier_bool+0xffffcf20>
80001440: 1e478793 addi a5,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
80001444: fec42703 lw a4,-20(s0)
80001448: 00e7aa23 sw a4,20(a5)
8000144c: fcc42703 lw a4,-52(s0)
80001450: fe842783 lw a5,-24(s0)
80001454: 02f76263 bltu a4,a5,80001478 <vx_e_mat_mult+0xe0>
80001458: 810267b7 lui a5,0x81026
8000145c: 20078693 addi a3,a5,512 # 81026200 <barrier_bool+0xffffcf20>
8000145c: 1e478693 addi a3,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
80001460: 800017b7 lui a5,0x80001
80001464: 4d078613 addi a2,a5,1232 # 800014d0 <barrier_bool+0xfefd81f0>
80001464: 4d078613 addi a2,a5,1232 # 800014d0 <barrier_bool+0xfefd820c>
80001468: fe842583 lw a1,-24(s0)
8000146c: fd042503 lw a0,-48(s0)
80001470: 804ff0ef jal ra,80000474 <vx_spawnWarps>
80001474: 0200006f j 80001494 <vx_e_mat_mult+0xfc>
80001478: 810267b7 lui a5,0x81026
8000147c: 20078693 addi a3,a5,512 # 81026200 <barrier_bool+0xffffcf20>
8000147c: 1e478693 addi a3,a5,484 # 810261e4 <barrier_bool+0xffffcf20>
80001480: 800017b7 lui a5,0x80001
80001484: 4d078613 addi a2,a5,1232 # 800014d0 <barrier_bool+0xfefd81f0>
80001484: 4d078613 addi a2,a5,1232 # 800014d0 <barrier_bool+0xfefd820c>
80001488: fcc42583 lw a1,-52(s0)
8000148c: fd042503 lw a0,-48(s0)
80001490: fe5fe0ef jal ra,80000474 <vx_spawnWarps>
@@ -1476,7 +1476,7 @@ Disassembly of section .text:
80001598: fc744783 lbu a5,-57(s0)
8000159c: 00078f13 mv t5,a5
800015a0: 800017b7 lui a5,0x80001
800015a4: 5f878f93 addi t6,a5,1528 # 800015f8 <barrier_bool+0xfefd8318>
800015a4: 5f878f93 addi t6,a5,1528 # 800015f8 <barrier_bool+0xfefd8334>
800015a8: 000f206b 0xf206b
800015ac: 01ff707b 0x1ff707b
800015b0: fcc42783 lw a5,-52(s0)
@@ -1495,7 +1495,7 @@ Disassembly of section .text:
800015e4: 00178793 addi a5,a5,1
800015e8: fef42423 sw a5,-24(s0)
800015ec: 800017b7 lui a5,0x80001
800015f0: 5fc78e13 addi t3,a5,1532 # 800015fc <barrier_bool+0xfefd831c>
800015f0: 5fc78e13 addi t3,a5,1532 # 800015fc <barrier_bool+0xfefd8338>
800015f4: 000e0067 jr t3
800015f8: 00000013 nop
800015fc: 0000306b 0x306b
@@ -1537,7 +1537,7 @@ Disassembly of section .text:
8000167c: fca42e23 sw a0,-36(s0)
80001680: fcb42c23 sw a1,-40(s0)
80001684: 810267b7 lui a5,0x81026
80001688: 21878713 addi a4,a5,536 # 81026218 <barrier_bool+0xffffcf38>
80001688: 1fc78713 addi a4,a5,508 # 810261fc <barrier_bool+0xffffcf38>
8000168c: fdc42783 lw a5,-36(s0)
80001690: 00f707b3 add a5,a4,a5
80001694: 00100713 li a4,1
@@ -1551,7 +1551,7 @@ Disassembly of section .text:
800016b4: fe042423 sw zero,-24(s0)
800016b8: 0340006f j 800016ec <barrier+0x80>
800016bc: 810267b7 lui a5,0x81026
800016c0: 21878713 addi a4,a5,536 # 81026218 <barrier_bool+0xffffcf38>
800016c0: 1fc78713 addi a4,a5,508 # 810261fc <barrier_bool+0xffffcf38>
800016c4: fe842783 lw a5,-24(s0)
800016c8: 00f707b3 add a5,a4,a5
800016cc: 0007c783 lbu a5,0(a5)
@@ -1571,17 +1571,17 @@ Disassembly of section .text:
80001704: fe042223 sw zero,-28(s0)
80001708: 0400006f j 80001748 <barrier+0xdc>
8000170c: 810267b7 lui a5,0x81026
80001710: 21878713 addi a4,a5,536 # 81026218 <barrier_bool+0xffffcf38>
80001710: 1fc78713 addi a4,a5,508 # 810261fc <barrier_bool+0xffffcf38>
80001714: fe442783 lw a5,-28(s0)
80001718: 00f707b3 add a5,a4,a5
8000171c: 00078023 sb zero,0(a5)
80001720: 810297b7 lui a5,0x81029
80001724: 00100713 li a4,1
80001728: 2ee78023 sb a4,736(a5) # 810292e0 <barrier_bool+0x0>
80001728: 2ce78223 sb a4,708(a5) # 810292c4 <barrier_bool+0x0>
8000172c: 04600513 li a0,70
80001730: efdff0ef jal ra,8000162c <sleep>
80001734: 810297b7 lui a5,0x81029
80001738: 2e078023 sb zero,736(a5) # 810292e0 <barrier_bool+0x0>
80001738: 2c078223 sb zero,708(a5) # 810292c4 <barrier_bool+0x0>
8000173c: fe442783 lw a5,-28(s0)
80001740: 00178793 addi a5,a5,1
80001744: fef42223 sw a5,-28(s0)
@@ -1593,7 +1593,7 @@ Disassembly of section .text:
8000175c: 0240006f j 80001780 <barrier+0x114>
80001760: 00000013 nop
80001764: 810297b7 lui a5,0x81029
80001768: 2e07c783 lbu a5,736(a5) # 810292e0 <barrier_bool+0x0>
80001768: 2c47c783 lbu a5,708(a5) # 810292c4 <barrier_bool+0x0>
8000176c: 0017c793 xori a5,a5,1
80001770: 0ff7f793 andi a5,a5,255
80001774: fe0798e3 bnez a5,80001764 <barrier+0xf8>
@@ -1614,14 +1614,14 @@ Disassembly of section .text:
800017a8: 810267b7 lui a5,0x81026
800017ac: fec42703 lw a4,-20(s0)
800017b0: 00271713 slli a4,a4,0x2
800017b4: 23878793 addi a5,a5,568 # 81026238 <barrier_bool+0xffffcf58>
800017b4: 21c78793 addi a5,a5,540 # 8102621c <barrier_bool+0xffffcf58>
800017b8: 00f707b3 add a5,a4,a5
800017bc: 00300713 li a4,3
800017c0: 00e7a023 sw a4,0(a5)
800017c4: 810277b7 lui a5,0x81027
800017c8: fec42703 lw a4,-20(s0)
800017cc: 00271713 slli a4,a4,0x2
800017d0: 23878793 addi a5,a5,568 # 81027238 <barrier_bool+0xffffdf58>
800017d0: 21c78793 addi a5,a5,540 # 8102721c <barrier_bool+0xffffdf58>
800017d4: 00f707b3 add a5,a4,a5
800017d8: 00200713 li a4,2
800017dc: 00e7a023 sw a4,0(a5)
@@ -1643,7 +1643,7 @@ Disassembly of section .text:
80001814: 03010413 addi s0,sp,48
80001818: fca42e23 sw a0,-36(s0)
8000181c: 810007b7 lui a5,0x81000
80001820: 11878513 addi a0,a5,280 # 81000118 <barrier_bool+0xfffd6e38>
80001820: 11878513 addi a0,a5,280 # 81000118 <barrier_bool+0xfffd6e54>
80001824: fb5fe0ef jal ra,800007d8 <vx_print_str>
80001828: fe042623 sw zero,-20(s0)
8000182c: 0580006f j 80001884 <print_matrix+0x7c>
@@ -1653,7 +1653,7 @@ Disassembly of section .text:
8000183c: 00f7f793 andi a5,a5,15
80001840: 00079863 bnez a5,80001850 <print_matrix+0x48>
80001844: 810007b7 lui a5,0x81000
80001848: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e5c>
80001848: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e78>
8000184c: f8dfe0ef jal ra,800007d8 <vx_print_str>
80001850: fec42783 lw a5,-20(s0)
80001854: 00279793 slli a5,a5,0x2
@@ -1663,7 +1663,7 @@ Disassembly of section .text:
80001864: 00078513 mv a0,a5
80001868: fadfe0ef jal ra,80000814 <vx_print_hex>
8000186c: 810007b7 lui a5,0x81000
80001870: 14078513 addi a0,a5,320 # 81000140 <barrier_bool+0xfffd6e60>
80001870: 14078513 addi a0,a5,320 # 81000140 <barrier_bool+0xfffd6e7c>
80001874: f65fe0ef jal ra,800007d8 <vx_print_str>
80001878: fec42783 lw a5,-20(s0)
8000187c: 00178793 addi a5,a5,1
@@ -1672,7 +1672,7 @@ Disassembly of section .text:
80001888: 0ff00793 li a5,255
8000188c: fae7d2e3 bge a5,a4,80001830 <print_matrix+0x28>
80001890: 810007b7 lui a5,0x81000
80001894: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e64>
80001894: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e80>
80001898: f41fe0ef jal ra,800007d8 <vx_print_str>
8000189c: 00000013 nop
800018a0: 02c12083 lw ra,44(sp)
@@ -1686,26 +1686,15 @@ Disassembly of section .text:
800018b8: 00812423 sw s0,8(sp)
800018bc: 01010413 addi s0,sp,16
800018c0: ed5ff0ef jal ra,80001794 <initialize_mats>
800018c4: 01000693 li a3,16
800018c8: 810287b7 lui a5,0x81028
800018cc: 23878613 addi a2,a5,568 # 81028238 <barrier_bool+0xffffef58>
800018d0: 810277b7 lui a5,0x81027
800018d4: 23878593 addi a1,a5,568 # 81027238 <barrier_bool+0xffffdf58>
800018d8: 810267b7 lui a5,0x81026
800018dc: 23878513 addi a0,a5,568 # 81026238 <barrier_bool+0xffffcf58>
800018e0: 840ff0ef jal ra,80000920 <vx_sq_mat_mult>
800018e4: 810007b7 lui a5,0x81000
800018e8: 16878513 addi a0,a5,360 # 81000168 <barrier_bool+0xfffd6e88>
800018ec: eedfe0ef jal ra,800007d8 <vx_print_str>
800018f0: 810287b7 lui a5,0x81028
800018f4: 23878513 addi a0,a5,568 # 81028238 <barrier_bool+0xffffef58>
800018f8: f11ff0ef jal ra,80001808 <print_matrix>
800018fc: 00000793 li a5,0
80001900: 00078513 mv a0,a5
80001904: 00c12083 lw ra,12(sp)
80001908: 00812403 lw s0,8(sp)
8000190c: 01010113 addi sp,sp,16
80001910: 00008067 ret
800018c4: 810267b7 lui a5,0x81026
800018c8: 21c78513 addi a0,a5,540 # 8102621c <barrier_bool+0xffffcf58>
800018cc: f3dff0ef jal ra,80001808 <print_matrix>
800018d0: 00000793 li a5,0
800018d4: 00078513 mv a0,a5
800018d8: 00c12083 lw ra,12(sp)
800018dc: 00812403 lw s0,8(sp)
800018e0: 01010113 addi sp,sp,16
800018e4: 00008067 ret
Disassembly of section .rodata:
@@ -1741,7 +1730,7 @@ Disassembly of section .rodata:
8100003e: 0000 unimp
81000040: 74696177 0x74696177
81000044: 6620 flw fs0,72(a2)
81000046: 203a726f jal tp,810a7a48 <barrier_bool+0x7e768>
81000046: 203a726f jal tp,810a7a48 <barrier_bool+0x7e784>
8100004a: 0000 unimp
8100004c: 6f46 flw ft10,80(sp)
8100004e: 6e75 lui t3,0x1d
@@ -1836,21 +1825,21 @@ Disassembly of section .rodata:
81000112: 0000 unimp
81000114: 0066 c.slli zero,0x19
81000116: 0000 unimp
81000118: 2d2d jal 81000752 <q+0x326>
8100011a: 2d2d jal 81000754 <q+0x328>
8100011c: 2d2d jal 81000756 <q+0x32a>
8100011e: 2d2d jal 81000758 <q+0x32c>
81000120: 2d2d jal 8100075a <q+0x32e>
81000122: 2d2d jal 8100075c <q+0x330>
81000124: 2d2d jal 8100075e <q+0x332>
81000126: 2d2d jal 81000760 <q+0x334>
81000128: 2d2d jal 81000762 <q+0x336>
8100012a: 2d2d jal 81000764 <q+0x338>
8100012c: 2d2d jal 81000766 <q+0x33a>
8100012e: 2d2d jal 81000768 <q+0x33c>
81000130: 2d2d jal 8100076a <q+0x33e>
81000132: 2d2d jal 8100076c <q+0x340>
81000134: 2d2d jal 8100076e <q+0x342>
81000118: 2d2d jal 81000752 <q+0x342>
8100011a: 2d2d jal 81000754 <q+0x344>
8100011c: 2d2d jal 81000756 <q+0x346>
8100011e: 2d2d jal 81000758 <q+0x348>
81000120: 2d2d jal 8100075a <q+0x34a>
81000122: 2d2d jal 8100075c <q+0x34c>
81000124: 2d2d jal 8100075e <q+0x34e>
81000126: 2d2d jal 81000760 <q+0x350>
81000128: 2d2d jal 81000762 <q+0x352>
8100012a: 2d2d jal 81000764 <q+0x354>
8100012c: 2d2d jal 81000766 <q+0x356>
8100012e: 2d2d jal 81000768 <q+0x358>
81000130: 2d2d jal 8100076a <q+0x35a>
81000132: 2d2d jal 8100076c <q+0x35c>
81000134: 2d2d jal 8100076e <q+0x35e>
81000136: 0a2d addi s4,s4,11
81000138: 0000 unimp
8100013a: 0000 unimp
@@ -1859,228 +1848,214 @@ Disassembly of section .rodata:
81000140: 0020 addi s0,sp,8
81000142: 0000 unimp
81000144: 2d0a fld fs10,128(sp)
81000146: 2d2d jal 81000780 <q+0x354>
81000148: 2d2d jal 81000782 <q+0x356>
8100014a: 2d2d jal 81000784 <q+0x358>
8100014c: 2d2d jal 81000786 <q+0x35a>
8100014e: 2d2d jal 81000788 <q+0x35c>
81000150: 2d2d jal 8100078a <q+0x35e>
81000152: 2d2d jal 8100078c <q+0x360>
81000154: 2d2d jal 8100078e <q+0x362>
81000156: 2d2d jal 81000790 <q+0x364>
81000158: 2d2d jal 81000792 <q+0x366>
8100015a: 2d2d jal 81000794 <q+0x368>
8100015c: 2d2d jal 81000796 <q+0x36a>
8100015e: 2d2d jal 81000798 <q+0x36c>
81000160: 2d2d jal 8100079a <q+0x36e>
81000162: 2d2d jal 8100079c <q+0x370>
81000146: 2d2d jal 81000780 <q+0x370>
81000148: 2d2d jal 81000782 <q+0x372>
8100014a: 2d2d jal 81000784 <q+0x374>
8100014c: 2d2d jal 81000786 <q+0x376>
8100014e: 2d2d jal 81000788 <q+0x378>
81000150: 2d2d jal 8100078a <q+0x37a>
81000152: 2d2d jal 8100078c <q+0x37c>
81000154: 2d2d jal 8100078e <q+0x37e>
81000156: 2d2d jal 81000790 <q+0x380>
81000158: 2d2d jal 81000792 <q+0x382>
8100015a: 2d2d jal 81000794 <q+0x384>
8100015c: 2d2d jal 81000796 <q+0x386>
8100015e: 2d2d jal 81000798 <q+0x388>
81000160: 2d2d jal 8100079a <q+0x38a>
81000162: 2d2d jal 8100079c <q+0x38c>
81000164: 000a c.slli zero,0x2
81000166: 0000 unimp
81000168: 0a0a slli s4,s4,0x2
8100016a: 614d addi sp,sp,176
8100016c: 7274 flw fa3,100(a2)
8100016e: 7869 lui a6,0xffffa
81000170: 6d20 flw fs0,88(a0)
81000172: 6c75 lui s8,0x1d
81000174: 6974 flw fa3,84(a0)
81000176: 6c70 flw fa2,92(s0)
81000178: 6369 lui t1,0x1a
8100017a: 7461 lui s0,0xffff8
8100017c: 6f69 lui t5,0x1a
8100017e: 0a6e slli s4,s4,0x1b
...
Disassembly of section .data:
81000184 <hextoa>:
81000184: 0000 unimp
81000168 <hextoa>:
81000168: 0000 unimp
8100016a: 8100 0x8100
8100016c: 0004 0x4
8100016e: 8100 0x8100
81000170: 0008 0x8
81000172: 8100 0x8100
81000174: 000c 0xc
81000176: 8100 0x8100
81000178: 0010 0x10
8100017a: 8100 0x8100
8100017c: 0014 0x14
8100017e: 8100 0x8100
81000180: 0018 0x18
81000182: 8100 0x8100
81000184: 001c 0x1c
81000186: 8100 0x8100
81000188: 0004 0x4
81000188: 0020 addi s0,sp,8
8100018a: 8100 0x8100
8100018c: 0008 0x8
8100018c: 0024 addi s1,sp,8
8100018e: 8100 0x8100
81000190: 000c 0xc
81000190: 0028 addi a0,sp,8
81000192: 8100 0x8100
81000194: 0010 0x10
81000194: 002c addi a1,sp,8
81000196: 8100 0x8100
81000198: 0014 0x14
81000198: 0030 addi a2,sp,8
8100019a: 8100 0x8100
8100019c: 0018 0x18
8100019c: 0034 addi a3,sp,8
8100019e: 8100 0x8100
810001a0: 001c 0x1c
810001a0: 0038 addi a4,sp,8
810001a2: 8100 0x8100
810001a4: 0020 addi s0,sp,8
810001a4: 003c addi a5,sp,8
810001a6: 8100 0x8100
810001a8: 0024 addi s1,sp,8
810001a8 <hextoa>:
810001a8: 0054 addi a3,sp,4
810001aa: 8100 0x8100
810001ac: 0028 addi a0,sp,8
810001ac: 0058 addi a4,sp,4
810001ae: 8100 0x8100
810001b0: 002c addi a1,sp,8
810001b0: 005c addi a5,sp,4
810001b2: 8100 0x8100
810001b4: 0030 addi a2,sp,8
810001b4: 0060 addi s0,sp,12
810001b6: 8100 0x8100
810001b8: 0034 addi a3,sp,8
810001b8: 0064 addi s1,sp,12
810001ba: 8100 0x8100
810001bc: 0038 addi a4,sp,8
810001bc: 0068 addi a0,sp,12
810001be: 8100 0x8100
810001c0: 003c addi a5,sp,8
810001c0: 006c addi a1,sp,12
810001c2: 8100 0x8100
810001c4 <hextoa>:
810001c4: 0054 addi a3,sp,4
810001c4: 0070 addi a2,sp,12
810001c6: 8100 0x8100
810001c8: 0058 addi a4,sp,4
810001c8: 0074 addi a3,sp,12
810001ca: 8100 0x8100
810001cc: 005c addi a5,sp,4
810001cc: 0078 addi a4,sp,12
810001ce: 8100 0x8100
810001d0: 0060 addi s0,sp,12
810001d0: 007c addi a5,sp,12
810001d2: 8100 0x8100
810001d4: 0064 addi s1,sp,12
810001d4: 0080 addi s0,sp,64
810001d6: 8100 0x8100
810001d8: 0068 addi a0,sp,12
810001d8: 0084 addi s1,sp,64
810001da: 8100 0x8100
810001dc: 006c addi a1,sp,12
810001dc: 0088 addi a0,sp,64
810001de: 8100 0x8100
810001e0: 0070 addi a2,sp,12
810001e0: 008c addi a1,sp,64
810001e2: 8100 0x8100
810001e4: 0074 addi a3,sp,12
810001e4: 0090 addi a2,sp,64
810001e6: 8100 0x8100
810001e8: 0078 addi a4,sp,12
810001e8 <hextoa>:
810001e8: 0098 addi a4,sp,64
810001ea: 8100 0x8100
810001ec: 007c addi a5,sp,12
810001ec: 009c addi a5,sp,64
810001ee: 8100 0x8100
810001f0: 0080 addi s0,sp,64
810001f0: 00a0 addi s0,sp,72
810001f2: 8100 0x8100
810001f4: 0084 addi s1,sp,64
810001f4: 00a4 addi s1,sp,72
810001f6: 8100 0x8100
810001f8: 0088 addi a0,sp,64
810001f8: 00a8 addi a0,sp,72
810001fa: 8100 0x8100
810001fc: 008c addi a1,sp,64
810001fc: 00ac addi a1,sp,72
810001fe: 8100 0x8100
81000200: 0090 addi a2,sp,64
81000200: 00b0 addi a2,sp,72
81000202: 8100 0x8100
81000204 <hextoa>:
81000204: 0098 addi a4,sp,64
81000204: 00b4 addi a3,sp,72
81000206: 8100 0x8100
81000208: 009c addi a5,sp,64
81000208: 00b8 addi a4,sp,72
8100020a: 8100 0x8100
8100020c: 00a0 addi s0,sp,72
8100020c: 00bc addi a5,sp,72
8100020e: 8100 0x8100
81000210: 00a4 addi s1,sp,72
81000210: 00c0 addi s0,sp,68
81000212: 8100 0x8100
81000214: 00a8 addi a0,sp,72
81000214: 00c4 addi s1,sp,68
81000216: 8100 0x8100
81000218: 00ac addi a1,sp,72
81000218: 00c8 addi a0,sp,68
8100021a: 8100 0x8100
8100021c: 00b0 addi a2,sp,72
8100021c: 00cc addi a1,sp,68
8100021e: 8100 0x8100
81000220: 00b4 addi a3,sp,72
81000220: 00d0 addi a2,sp,68
81000222: 8100 0x8100
81000224: 00b8 addi a4,sp,72
81000224: 00d4 addi a3,sp,68
81000226: 8100 0x8100
81000228: 00bc addi a5,sp,72
8100022a: 8100 0x8100
8100022c: 00c0 addi s0,sp,68
8100022e: 8100 0x8100
81000230: 00c4 addi s1,sp,68
81000232: 8100 0x8100
81000234: 00c8 addi a0,sp,68
81000236: 8100 0x8100
81000238: 00cc addi a1,sp,68
8100023a: 8100 0x8100
8100023c: 00d0 addi a2,sp,68
8100023e: 8100 0x8100
81000240: 00d4 addi a3,sp,68
81000242: 8100 0x8100
81000244 <hextoa>:
81000244: 00d8 addi a4,sp,68
81000228 <hextoa>:
81000228: 00d8 addi a4,sp,68
8100022a: 8100 0x8100
8100022c: 00dc addi a5,sp,68
8100022e: 8100 0x8100
81000230: 00e0 addi s0,sp,76
81000232: 8100 0x8100
81000234: 00e4 addi s1,sp,76
81000236: 8100 0x8100
81000238: 00e8 addi a0,sp,76
8100023a: 8100 0x8100
8100023c: 00ec addi a1,sp,76
8100023e: 8100 0x8100
81000240: 00f0 addi a2,sp,76
81000242: 8100 0x8100
81000244: 00f4 addi a3,sp,76
81000246: 8100 0x8100
81000248: 00dc addi a5,sp,68
81000248: 00f8 addi a4,sp,76
8100024a: 8100 0x8100
8100024c: 00e0 addi s0,sp,76
8100024c: 00fc addi a5,sp,76
8100024e: 8100 0x8100
81000250: 00e4 addi s1,sp,76
81000250: 0100 addi s0,sp,128
81000252: 8100 0x8100
81000254: 00e8 addi a0,sp,76
81000254: 0104 addi s1,sp,128
81000256: 8100 0x8100
81000258: 00ec addi a1,sp,76
81000258: 0108 addi a0,sp,128
8100025a: 8100 0x8100
8100025c: 00f0 addi a2,sp,76
8100025c: 010c addi a1,sp,128
8100025e: 8100 0x8100
81000260: 00f4 addi a3,sp,76
81000260: 0110 addi a2,sp,128
81000262: 8100 0x8100
81000264: 00f8 addi a4,sp,76
81000264: 0114 addi a3,sp,128
81000266: 8100 0x8100
81000268: 00fc addi a5,sp,76
8100026a: 8100 0x8100
8100026c: 0100 addi s0,sp,128
8100026e: 8100 0x8100
81000270: 0104 addi s1,sp,128
81000272: 8100 0x8100
81000274: 0108 addi a0,sp,128
81000276: 8100 0x8100
81000278: 010c addi a1,sp,128
8100027a: 8100 0x8100
8100027c: 0110 addi a2,sp,128
8100027e: 8100 0x8100
81000280: 0114 addi a3,sp,128
81000282: 8100 0x8100
Disassembly of section .bss:
81000284 <done>:
81000268 <done>:
...
81000328 <main_sp>:
81000328: 0000 unimp
8100030c <main_sp>:
8100030c: 0000 unimp
...
8100032c <context>:
81000310 <context>:
...
8100042c <q>:
81000410 <q>:
...
8102612c <done>:
81026110 <done>:
...
810261d0 <main_sp>:
810261d0: 0000 unimp
810261b4 <main_sp>:
810261b4: 0000 unimp
...
810261d4 <mat_mult_args>:
810261b8 <mat_mult_args>:
...
810261e8 <mat_r_args>:
810261cc <mat_r_args>:
...
81026200 <mat_e_args>:
810261e4 <mat_e_args>:
...
81026218 <barriers>:
810261fc <barriers>:
...
81026238 <x>:
8102621c <x>:
...
81027238 <y>:
8102721c <y>:
...
81028238 <z>:
8102821c <z>:
...
81029238 <done>:
8102921c <done>:
...
810292dc <main_sp>:
810292dc: 0000 unimp
810292c0 <main_sp>:
810292c0: 0000 unimp
...
Disassembly of section .sbss:
810292e0 <barrier_bool>:
810292c4 <barrier_bool>:
...
Disassembly of section .comment:

BIN
kernel/vortex_test.elf
View File

Binary file not shown.

161
kernel/vortex_test.hex
View File

@@ -12,7 +12,7 @@
:1000A0001300000013000000130000001300000004
:1000B0001300000013000000170500001305451B86
:1000C0006B40050017030000130343F66B000300A9
:1000D000678000001702000113028225232002001E
:1000D00067800000170200011302C22323200200E0
:1000E0002322120023242200232632002328420048
:1000F000232A5200232C6200232E72002320820226
:10010000232292022324A2022326B2022328C2021F
@@ -21,7 +21,7 @@
:10013000232A5205232C6205232E720523208207D1
:10014000232292072324A2072326B2072328C207CB
:10015000232AD207232CE207232EF20713021000D2
:1001600067800000170200011302821C03200200B6
:1001600067800000170200011302C21A0320020078
:1001700083204200032182008321C2000322020166
:1001800083224201032382018323C201032402024A
:1001900083244202032582028325C202032602032E
@@ -34,19 +34,19 @@
:1002000067800000130101FE232E1100232C8100C2
:1002100013040102232604FE6F0040030327C4FEDB
:10022000B7170000938747973307F702B707008196
:100230009387C742B307F70013850700EF00004418
:1002300093870741B307F70013850700EF000044D9
:100240008327C4FE938717002326F4FE0327C4FEEA
:100250009307F001E3D4E7FC130000008320C10101
:10026000032481011301010267800000130101FDD5
:1002700023261102232481022322A1031304010354
:100280001300000013070D00B7170000938747976E
:100290003307F702B70700819387C742B307F70018
:100290003307F702B707008193870741B307F700D9
:1002A00013850700EF00405093070500638A07029B
:1002B00013070D00B70700811317270093874728FE
:1002B00013070D00B70700811317270093878726C0
:1002C000B307F7001307100023A0E70093070D0002
:1002D00063960700EFF01FE96F00C0057300000090
:1002E00013070D00B7170000938747973307F702EE
:1002F000B70700819387C742B307F700130784FD50
:1002F000B707008193870741B307F700130784FD11
:100300009305070013850700EF000040832704FED4
:10031000138107008327C4FD832584FD032644FE43
:10032000832684FE0327C4FE13850700EFF0DFCF8A
@@ -55,18 +55,18 @@
:100350002324810413040105EFF0DFE92324A4FE24
:1003600093090100930710002326F4FE6F00C008D4
:100370000327C4FEB7170000938747973307F70298
:10038000B70700819387C742B307F70013850700BB
:10038000B707008193870741B307F700138507007C
:10039000EF00804193070500639A07040327C4FE1A
:1003A000B7170000938747973307F702B707008115
:1003B0009387C742B307F700130704FD93050700AF
:1003B00093870741B307F700130704FD9305070070
:1003C00013850700EF004034832784FD1381070065
:1003D000832744FD832504FD0326C4FD832604FEF4
:1003E000032744FE13850700EFF0DFCD8327C4FE0B
:1003F000938717002326F4FE8327C4FE032784FE79
:10040000E3E8E7F613810900EFF0DFCC9307020081
:1004100063880704B70700811385C742EF00C0381F
:1004100063880704B707008113850741EF00C038E0
:1004200093070500639E0702930784FB93850700EB
:10043000B70700811385C742EF00002D832704FC16
:10043000B707008113850741EF00002D832704FCD7
:10044000138107008327C4FB832584FB032644FC18
:10045000832684FC0327C4FC13850700EFF0DFBC70
:10046000130000008320C10403248104130101054B
@@ -78,7 +78,7 @@
:1004C000832784FB2328F4FC93070100232AF4FCF0
:1004D000832744FB232CF4FC832704FB232EF4FC0A
:1004E0008327C4FE2320F4FE0327C4FEB7170000B1
:1004F000938747973307F702B70700819387C7426F
:1004F000938747973307F702B70700819387074130
:10050000B307F7001307C4FC930507001385070022
:10051000EF0000198327C4FE938717002326F4FEFB
:100520008327C4FE032744FE63E4E700232604FE7A
@@ -90,13 +90,13 @@
:1005800013850704EF004035EFF0DFC62320A4FEFB
:10059000232604FE6F008006930710002326F4FE36
:1005A000232404FE6F00C003B7070081032784FEE5
:1005B0001317270093874728B307F70003A70700FF
:1005B0001317270093878726B307F70003A70700C1
:1005C000930710006318F7008327C4FE9387170072
:1005D0002326F4FE832784FE938717002324F4FE4A
:1005E000032784FE9307F001E3D0E7FC8325C4FED4
:1005F000B70700811385C704EF00002E0327C4FE50
:100600008327C4FDE36AF7F8232204FE6F0080020B
:10061000B7070081032744FE131727009387472855
:10061000B7070081032744FE131727009387872617
:10062000B307F70023A00700832744FE9387170032
:100630002322F4FE832744FE032704FEE3EAE7FCBB
:10064000130000008320C10203248102130101036F
@@ -131,13 +131,13 @@
:1008100067800000130101FD2326110223248102B9
:1008200013040103232EA4FC0327C4FD9307F00047
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@@ -147,18 +147,18 @@
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@@ -190,18 +190,18 @@
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@@ -274,18 +274,18 @@
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@@ -315,18 +315,18 @@
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@@ -359,28 +359,28 @@
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@@ -395,12 +395,9 @@
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@@ -424,24 +421,22 @@
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8
kernel/vx_main.c
View File

@@ -37,9 +37,11 @@ int main()
initialize_mats();
// matrix multiplication
vx_sq_mat_mult(x, y, z, MAT_DIM);
vx_print_str("\n\nMatrix multiplication\n");
print_matrix(z);
// vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z);
print_matrix(x);
// // matrix addition

2
rtl/VX_decode.v
View File

@@ -165,7 +165,7 @@ module VX_decode(
.VX_gpr_jal (VX_gpr_jal),
.VX_gpr_clone (VX_gpr_clone),
.VX_gpr_wspawn (VX_gpr_wspawn),
.out_a_reg_data (VX_frE_to_bckE_req.a_reg_data),
.out_b_reg_data (VX_frE_to_bckE_req.b_reg_data),
.out_clone_stall(out_clone_stall)

42
rtl/VX_gpr.v
View File

@@ -1,8 +1,42 @@
`include "VX_define.v"
module VX_gpr (
input clk, // Clock
input clk_en, // Clock Enable
input rst_n, // Asynchronous reset active low
input wire clk,
input wire valid_write_request,
input wire valid_read_request,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
output reg[`NT_M1:0][31:0] out_a_reg_data,
output reg[`NT_M1:0][31:0] out_b_reg_data
);
logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// assign read_enable = valid_request;
genvar thread_index;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
if (VX_writeback_inter.wb_valid[thread_index]) begin
gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
end
end
end
end
always @(negedge clk) begin
if (valid_read_request) begin
out_a_reg_data <= gpr[VX_gpr_read.rs1];
out_b_reg_data <= gpr[VX_gpr_read.rs2];
end
end
endmodule

148
rtl/VX_gpr_wrapper.v
View File

@@ -2,9 +2,10 @@
module VX_gpr_wrapper (
input wire clk,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
VX_forward_response_inter VX_fwd_rsp,
VX_gpr_read_inter VX_gpr_read,
VX_gpr_jal_inter VX_gpr_jal,
VX_gpr_clone_inter VX_gpr_clone,
VX_gpr_wspawn_inter VX_gpr_wspawn,
@@ -15,81 +16,102 @@ module VX_gpr_wrapper (
);
wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] temp_a_reg_data;
wire[`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data));
assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data);
assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
wire[31:0][31:0] w0_t0_registers;
wire[`NW-1:0] temp_clone_stall;
wire[`NW-1:0] temp_clone_stall = 0;
assign out_clone_stall = (|temp_clone_stall);
wire curr_warp_zero = VX_gpr_read.warp_num == 0;
wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0);
VX_context VX_Context_zero(
.clk (clk),
.in_warp (curr_warp_zero),
.in_wb_warp (context_zero_valid),
.in_valid (VX_writeback_inter.wb_valid),
.in_rd (VX_writeback_inter.rd),
.in_src1 (VX_gpr_read.rs1),
.in_src2 (VX_gpr_read.rs2),
.in_is_clone (real_zero_isclone),
.in_src1_fwd (VX_fwd_rsp.src1_fwd),
.in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
.in_src2_fwd (VX_fwd_rsp.src2_fwd),
.in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
.in_write_register(write_register),
.in_write_data (VX_writeback_inter.write_data),
.out_a_reg_data (temp_a_reg_data[0]),
.out_b_reg_data (temp_b_reg_data[0]),
.out_clone_stall (temp_clone_stall[0]),
.w0_t0_registers (w0_t0_registers)
);
genvar r;
genvar warp_index;
generate
for (r = 1; r < `NW; r = r + 1) begin
wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r);
wire curr_warp_glob = VX_gpr_read.warp_num == r;
wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r);
wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r);
VX_context_slave VX_Context_one(
.clk (clk),
.in_warp (curr_warp_glob),
.in_wb_warp (context_glob_valid),
.in_valid (VX_writeback_inter.wb_valid),
.in_rd (VX_writeback_inter.rd),
.in_src1 (VX_gpr_read.rs1),
.in_src2 (VX_gpr_read.rs2),
.in_is_clone (real_isclone),
.in_src1_fwd (VX_fwd_rsp.src1_fwd),
.in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
.in_src2_fwd (VX_fwd_rsp.src2_fwd),
.in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
.in_write_register(write_register),
.in_write_data (VX_writeback_inter.write_data),
.in_wspawn_regs (w0_t0_registers),
.in_wspawn (real_wspawn),
.out_a_reg_data (temp_a_reg_data[r]),
.out_b_reg_data (temp_b_reg_data[r]),
.out_clone_stall (temp_clone_stall[r])
);
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
wire valid_read_request = warp_index == VX_gpr_read.warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.valid_read_request (valid_read_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data),
.out_b_reg_data (temp_b_reg_data)
);
end
endgenerate
// wire[31:0][31:0] w0_t0_registers;
// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
// wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0);
// VX_context VX_Context_zero(
// .clk (clk),
// .in_warp (curr_warp_zero),
// .in_wb_warp (context_zero_valid),
// .in_valid (VX_writeback_inter.wb_valid),
// .in_rd (VX_writeback_inter.rd),
// .in_src1 (VX_gpr_read.rs1),
// .in_src2 (VX_gpr_read.rs2),
// .in_is_clone (real_zero_isclone),
// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
// .in_write_register(write_register),
// .in_write_data (VX_writeback_inter.write_data),
// .out_a_reg_data (temp_a_reg_data[0]),
// .out_b_reg_data (temp_b_reg_data[0]),
// .out_clone_stall (temp_clone_stall[0]),
// .w0_t0_registers (w0_t0_registers)
// );
// genvar r;
// generate
// for (r = 1; r < `NW; r = r + 1) begin
// wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r);
// wire curr_warp_glob = VX_gpr_read.warp_num == r;
// wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r);
// wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r);
// VX_context_slave VX_Context_one(
// .clk (clk),
// .in_warp (curr_warp_glob),
// .in_wb_warp (context_glob_valid),
// .in_valid (VX_writeback_inter.wb_valid),
// .in_rd (VX_writeback_inter.rd),
// .in_src1 (VX_gpr_read.rs1),
// .in_src2 (VX_gpr_read.rs2),
// .in_is_clone (real_isclone),
// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
// .in_write_register(write_register),
// .in_write_data (VX_writeback_inter.write_data),
// .in_wspawn_regs (w0_t0_registers),
// .in_wspawn (real_wspawn),
// .out_a_reg_data (temp_a_reg_data[r]),
// .out_b_reg_data (temp_b_reg_data[r]),
// .out_clone_stall (temp_clone_stall[r])
// );
// end
// endgenerate
endmodule

3
rtl/interfaces/VX_gpr_clone_inter.v
View File

@@ -5,9 +5,10 @@
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (

2
rtl/interfaces/VX_gpr_jal_inter.v
View File

@@ -5,11 +5,9 @@
interface VX_gpr_jal_inter ();
wire is_jal;
wire[31:0] curr_PC;
modport snk (
input is_jal,
input curr_PC

13
rtl/interfaces/VX_gpr_read_inter.sv
View File

@@ -10,19 +10,6 @@ interface VX_gpr_read_inter ();
wire[4:0] rs2;
wire[`NW_M1:0] warp_num;
modport snk (
input rs1,
input rs2,
input warp_num
);
modport src (
output rs1,
output rs2,
output warp_num
);
endinterface

3
rtl/interfaces/VX_gpr_wspawn_inter.v
View File

@@ -5,10 +5,11 @@
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire[`NW_M1:0] which_wspawn;
// wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (

BIN
rtl/obj_dir/VVortex
View File

Binary file not shown.

6987
rtl/obj_dir/VVortex.cpp
View File

File diff suppressed because it is too large Load Diff

263
rtl/obj_dir/VVortex.h
View File

@@ -89,7 +89,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_clone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_wspawn,0,0);
@@ -99,42 +98,15 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jmprt_thread_mask,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_ebreak,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_clone_stall,7,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__real_zero_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__real_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__real_isclone,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
@@ -154,6 +126,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
@@ -164,59 +138,9 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
};
struct {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__rd1_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__rd2_register,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
@@ -225,8 +149,6 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,463,0,15);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,302,0,10);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next,127,0,4);
@@ -257,125 +179,52 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__VX_Context_zero__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__VX_Context_zero__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data,127,0,4);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
};
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
@@ -411,7 +260,7 @@ VL_MODULE(VVortex) {
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__11(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
@@ -428,7 +277,7 @@ VL_MODULE(VVortex) {
static void _multiclk__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;

2
rtl/obj_dir/VVortex_VX_wb_inter.cpp
View File

@@ -30,7 +30,7 @@ VVortex_VX_wb_inter::~VVortex_VX_wb_inter() {
// Internal Methods
void VVortex_VX_wb_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_wb_inter::_ctor_var_reset\n"); );
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_wb_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,write_data);
}

BIN
rtl/obj_dir/VVortex__ALL.a
View File

Binary file not shown.

BIN
rtl/obj_dir/VVortex__ALLcls.o
View File

Binary file not shown.

2
rtl/obj_dir/VVortex__ver.d
View File

@@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr_wrapper.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.sv interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.sv interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v

72
rtl/obj_dir/VVortex__verFiles.dat
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@@ -3,21 +3,17 @@ C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
S 2767 1703128 1567984522 0 1567984522 0 "VX_back_end.v"
S 3130 890783 1568051338 0 1568051338 0 "VX_context.v"
S 4891 890784 1568051394 0 1568051394 0 "VX_context_slave.v"
S 1837 1768199 1567984564 0 1567984564 0 "VX_csr_handler.v"
S 13386 890775 1568052206 0 1568052206 0 "VX_decode.v"
S 13387 891321 1568075916 0 1568075916 0 "VX_decode.v"
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
S 3835 1573272 1567973378 0 1567973378 0 "VX_execute.v"
S 3835 891130 1568052328 0 1568052328 0 "VX_execute.v"
S 6520 1598760 1567980382 0 1567980382 0 "VX_fetch.v"
S 6148 1701713 1567982096 0 1567982096 0 "VX_forwarding.v"
S 2719 1701603 1567981038 0 1567981038 0 "VX_front_end.v"
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
S 3369 890722 1568052140 0 1568052140 0 "VX_gpr_wrapper.v"
S 1147 891129 1568081586 0 1568081586 0 "VX_gpr.v"
S 4212 891132 1568081646 0 1568081646 0 "VX_gpr_wrapper.v"
S 2584 1768087 1567983338 0 1567983338 0 "VX_memory.v"
S 1249 1572596 1567702894 0 1567702894 0 "VX_register_file.v"
S 1655 1572598 1567702916 0 1567702916 0 "VX_register_file_master_slave.v"
S 1599 1572597 1567702888 0 1567702888 0 "VX_register_file_slave.v"
S 1915 1565256 1567474434 0 1567474434 0 "VX_warp.v"
S 1597 1704649 1567981924 0 1567981924 0 "VX_writeback.v"
S 4392 1703129 1567985238 0 1567985238 0 "Vortex.v"
@@ -31,10 +27,10 @@ S 377 1582724 1567978250 0 1567978250 0 "interfaces
S 520 1573373 1567970758 0 1567970758 0 "interfaces//VX_forward_response_inter.v"
S 595 1573167 1567968126 0 1567968126 0 "interfaces//VX_forward_wb_inter.v"
S 1689 1571958 1567565366 0 1567565366 0 "interfaces//VX_frE_to_bckE_req_inter.v"
S 281 890852 1568051756 0 1568051756 0 "interfaces//VX_gpr_clone_inter.v"
S 258 890721 1568051502 0 1568051502 0 "interfaces//VX_gpr_jal_inter.v"
S 298 890642 1568050686 0 1568050686 0 "interfaces//VX_gpr_read_inter.sv"
S 328 890877 1568052200 0 1568052200 0 "interfaces//VX_gpr_wspawn_inter.v"
S 345 891319 1568075890 0 1568075890 0 "interfaces//VX_gpr_clone_inter.v"
S 256 891318 1568075982 0 1568075982 0 "interfaces//VX_gpr_jal_inter.v"
S 168 891192 1568075672 0 1568075672 0 "interfaces//VX_gpr_read_inter.sv"
S 392 891320 1568075898 0 1568075898 0 "interfaces//VX_gpr_wspawn_inter.v"
S 279 1578590 1567975102 0 1567975102 0 "interfaces//VX_icache_request_inter.v"
S 315 1578593 1567975152 0 1567975152 0 "interfaces//VX_icache_response_inter.v"
S 679 1573336 1567972210 0 1567972210 0 "interfaces//VX_inst_mem_wb_inter.v"
@@ -44,32 +40,32 @@ S 995 1572568 1567701364 0 1567701364 0 "interfaces
S 654 1573355 1567969270 0 1567969270 0 "interfaces//VX_mw_wb_inter.v"
S 603 1571976 1567568452 0 1567568452 0 "interfaces//VX_warp_ctl_inter.v"
S 459 890638 1568049504 0 1568049504 0 "interfaces//VX_wb_inter.v"
T 1268581 890659 1568052208 0 1568052208 0 "obj_dir/VVortex.cpp"
T 47834 890653 1568052208 0 1568052208 0 "obj_dir/VVortex.h"
T 1791 890788 1568052208 0 1568052208 0 "obj_dir/VVortex.mk"
T 914 890758 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 890757 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 890754 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 890753 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 890752 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 890751 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1059 890756 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1142 890755 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 890786 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 890780 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 890767 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 890763 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 890769 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 890768 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 890762 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 890761 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 823 890760 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 890759 1568052208 0 1568052208 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 890648 1568052208 0 1568052208 0 "obj_dir/VVortex__Syms.cpp"
T 1855 890647 1568052208 0 1568052208 0 "obj_dir/VVortex__Syms.h"
T 2151 890789 1568052208 0 1568052208 0 "obj_dir/VVortex__ver.d"
T 0 0 1568052208 0 1568052208 0 "obj_dir/VVortex__verFiles.dat"
T 1530 890787 1568052208 0 1568052208 0 "obj_dir/VVortex_classes.mk"
T 664405 891161 1568081662 0 1568081662 0 "obj_dir/VVortex.cpp"
T 21432 891159 1568081662 0 1568081662 0 "obj_dir/VVortex.h"
T 1791 891296 1568081662 0 1568081662 0 "obj_dir/VVortex.mk"
T 914 891284 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 891283 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 891176 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 891173 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 891156 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 891154 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1059 891282 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1142 891185 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 891292 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 891291 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 891288 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 891287 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 891290 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 891289 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 891286 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 891285 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 891294 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 891293 1568081662 0 1568081662 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 891142 1568081662 0 1568081662 0 "obj_dir/VVortex__Syms.cpp"
T 1855 891137 1568081662 0 1568081662 0 "obj_dir/VVortex__Syms.h"
T 2052 891297 1568081662 0 1568081662 0 "obj_dir/VVortex__ver.d"
T 0 0 1568081662 0 1568081662 0 "obj_dir/VVortex__verFiles.dat"
T 1530 891295 1568081662 0 1568081662 0 "obj_dir/VVortex_classes.mk"
S 6179 1572602 1567698562 0 1567698562 0 "pipe_regs//VX_d_e_reg.v"
S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v"
S 755 1591921 1567978394 0 1567978394 0 "pipe_regs//VX_f_d_reg.v"

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rtl/obj_dir/test_bench.o
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8
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 173969
# of total cycles: 175806
# Dynamic Instructions: 47217
# of total cycles: 47224
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01056
# time to simulate: 2.15982e-314 milliseconds
# CPI: 1.00015
# time to simulate: 2.17e-314 milliseconds
# GRADE: Failed on test: 4294967295