117 lines
4.1 KiB
Verilog
117 lines
4.1 KiB
Verilog
`include "VX_define.v"
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module VX_gpr_wrapper (
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input wire clk,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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VX_forward_response_inter VX_fwd_rsp,
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VX_gpr_jal_inter VX_gpr_jal,
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VX_gpr_clone_inter VX_gpr_clone,
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VX_gpr_wspawn_inter VX_gpr_wspawn,
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output wire[`NT_M1:0][31:0] out_a_reg_data,
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output wire[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_clone_stall
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);
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wire[`NT_M1:0][31:0] temp_a_reg_data;
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wire[`NT_M1:0][31:0] temp_b_reg_data;
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wire[`NT_M1:0][31:0] jal_data;
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
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assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data));
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assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data);
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wire[`NW-1:0] temp_clone_stall = 0;
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assign out_clone_stall = (|temp_clone_stall);
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genvar warp_index;
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generate
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for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
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wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
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wire valid_read_request = warp_index == VX_gpr_read.warp_num;
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VX_gpr vx_gpr(
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.clk (clk),
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.valid_write_request(valid_write_request),
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.valid_read_request (valid_read_request),
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.VX_gpr_read (VX_gpr_read),
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.VX_writeback_inter (VX_writeback_inter),
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.out_a_reg_data (temp_a_reg_data),
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.out_b_reg_data (temp_b_reg_data)
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);
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end
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endgenerate
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// wire[31:0][31:0] w0_t0_registers;
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// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
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// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
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// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
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// wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0);
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// VX_context VX_Context_zero(
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// .clk (clk),
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// .in_warp (curr_warp_zero),
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// .in_wb_warp (context_zero_valid),
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// .in_valid (VX_writeback_inter.wb_valid),
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// .in_rd (VX_writeback_inter.rd),
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// .in_src1 (VX_gpr_read.rs1),
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// .in_src2 (VX_gpr_read.rs2),
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// .in_is_clone (real_zero_isclone),
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// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
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// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
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// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
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// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
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// .in_write_register(write_register),
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// .in_write_data (VX_writeback_inter.write_data),
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// .out_a_reg_data (temp_a_reg_data[0]),
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// .out_b_reg_data (temp_b_reg_data[0]),
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// .out_clone_stall (temp_clone_stall[0]),
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// .w0_t0_registers (w0_t0_registers)
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// );
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// genvar r;
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// generate
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// for (r = 1; r < `NW; r = r + 1) begin
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// wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r);
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// wire curr_warp_glob = VX_gpr_read.warp_num == r;
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// wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r);
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// wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r);
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// VX_context_slave VX_Context_one(
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// .clk (clk),
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// .in_warp (curr_warp_glob),
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// .in_wb_warp (context_glob_valid),
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// .in_valid (VX_writeback_inter.wb_valid),
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// .in_rd (VX_writeback_inter.rd),
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// .in_src1 (VX_gpr_read.rs1),
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// .in_src2 (VX_gpr_read.rs2),
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// .in_is_clone (real_isclone),
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// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
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// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
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// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
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// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
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// .in_write_register(write_register),
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// .in_write_data (VX_writeback_inter.write_data),
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// .in_wspawn_regs (w0_t0_registers),
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// .in_wspawn (real_wspawn),
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// .out_a_reg_data (temp_a_reg_data[r]),
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// .out_b_reg_data (temp_b_reg_data[r]),
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// .out_clone_stall (temp_clone_stall[r])
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// );
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// end
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// endgenerate
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endmodule |