26 lines
256 B
Verilog
26 lines
256 B
Verilog
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`ifndef VX_GPR_JAL_INTER
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`define VX_GPR_JAL_INTER
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interface VX_gpr_jal_inter ();
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wire is_jal;
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wire[31:0] curr_PC;
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modport snk (
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input is_jal,
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input curr_PC
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);
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modport src (
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output is_jal,
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output curr_PC
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);
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endinterface
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`endif |