101 lines
3.2 KiB
Verilog
101 lines
3.2 KiB
Verilog
`include "VX_cache_define.vh"
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module VX_data_access #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_UNUSED_BEGIN
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input wire[31:0] debug_pc,
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input wire[`NW_BITS-1:0] debug_wid,
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`IGNORE_UNUSED_END
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`endif
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input wire stall,
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`IGNORE_UNUSED_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] addr,
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`IGNORE_UNUSED_END
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// reading
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input wire readen,
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output wire [`CACHE_LINE_WIDTH-1:0] read_data,
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// writing
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input wire writeen,
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input wire is_fill,
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input wire [CACHE_LINE_SIZE-1:0] byteen,
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input wire [`CACHE_LINE_WIDTH-1:0] write_data,
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input wire [`CACHE_LINE_WIDTH-1:0] fill_data
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);
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`UNUSED_PARAM (CACHE_ID)
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`UNUSED_PARAM (BANK_ID)
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`UNUSED_PARAM (WORD_SIZE)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (readen)
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localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
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wire [`LINE_SELECT_BITS-1:0] line_addr;
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wire [`CACHE_LINE_WIDTH-1:0] wdata;
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wire [BYTEENW-1:0] wren;
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assign line_addr = addr[`LINE_SELECT_BITS-1:0];
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if (WRITE_ENABLE) begin
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assign wren = is_fill ? {BYTEENW{writeen}} : (byteen & {BYTEENW{writeen}});
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assign wdata = is_fill ? fill_data : write_data;
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end else begin
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`UNUSED_VAR (is_fill)
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`UNUSED_VAR (byteen)
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`UNUSED_VAR (write_data)
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assign wren = writeen;
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assign wdata = fill_data;
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end
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VX_sp_ram #(
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.DATAW (CACHE_LINE_SIZE * 8),
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.SIZE (`LINES_PER_BANK),
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.BYTEENW (BYTEENW),
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.NO_RWCHECK (1)
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) data_store (
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.clk (clk),
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.addr (line_addr),
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.wren (wren),
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.wdata (wdata),
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.rden (1'b1),
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.rdata (read_data)
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);
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`UNUSED_VAR (stall)
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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if (writeen && ~stall) begin
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if (is_fill) begin
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dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);
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end else begin
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dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, wren, line_addr, write_data);
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end
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end
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if (readen && ~stall) begin
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dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data);
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end
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end
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`endif
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endmodule |