230 lines
9.8 KiB
Verilog
230 lines
9.8 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Socket (
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// Clock
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input wire clk,
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input wire reset,
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// DRAM Req
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output wire dram_req_read,
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output wire dram_req_write,
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output wire[`L3DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire[`L3DRAM_LINE_WIDTH-1:0] dram_req_data,
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output wire[`L3DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM Rsp
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input wire dram_rsp_valid,
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input wire[`L3DRAM_LINE_WIDTH-1:0] dram_rsp_data,
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input wire[`L3DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Cache Snooping
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input wire llc_snp_req_valid,
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input wire[`L3DRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
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output wire llc_snp_req_ready,
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// I/O
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output wire io_valid,
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output wire [31:0] io_data,
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input wire io_ready,
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// Debug
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output wire ebreak
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);
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if (`NUM_CLUSTERS == 1) begin
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Vortex_Cluster #(
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.CLUSTER_ID(0)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_ready (dram_rsp_ready),
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.llc_snp_req_valid (llc_snp_req_valid),
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.llc_snp_req_addr (llc_snp_req_addr),
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.llc_snp_req_ready (llc_snp_req_ready),
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.io_valid (io_valid),
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.io_data (io_data),
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.io_ready (io_ready),
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.ebreak (ebreak)
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);
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end else begin
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// DRAM Dcache Req
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
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wire l3_core_req_ready;
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// DRAM Dcache Rsp
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
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wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data;
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wire[`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
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wire snp_fwd_valid;
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wire[`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
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wire[`NUM_CLUSTERS-1:0] per_cluster_snp_fwd_ready;
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`IGNORE_WARNINGS_BEGIN
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wire[`NUM_CLUSTERS-1:0] per_cluster_io_valid;
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wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_data;
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`IGNORE_WARNINGS_END
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wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
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assign io_valid = per_cluster_io_valid[0];
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assign io_data = per_cluster_io_data[0];
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assign ebreak = (& per_cluster_ebreak);
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genvar i;
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for (i = 0; i < `NUM_CLUSTERS; i=i+1) begin
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Vortex_Cluster #(
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.CLUSTER_ID(i)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.dram_req_write (per_cluster_dram_req_write [i]),
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.dram_req_read (per_cluster_dram_req_read [i]),
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.dram_req_addr (per_cluster_dram_req_addr [i]),
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.dram_req_data (per_cluster_dram_req_data [i]),
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.dram_req_tag (per_cluster_dram_req_tag [i]),
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.dram_req_ready (l3_core_req_ready),
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.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
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.dram_rsp_data (per_cluster_dram_rsp_data [i]),
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.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
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.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
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.llc_snp_req_valid (snp_fwd_valid),
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.llc_snp_req_addr (snp_fwd_addr),
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.llc_snp_req_ready (per_cluster_snp_fwd_ready [i]),
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.io_valid (per_cluster_io_valid [i]),
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.io_data (per_cluster_io_data [i]),
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.io_ready (io_ready),
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.ebreak (per_cluster_ebreak [i])
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);
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end
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// L3 Cache ///////////////////////////////////////////////////////////
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wire[`L3NUM_REQUESTS-1:0] l3_core_req_valid;
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wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_read;
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wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_write;
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wire[`L3NUM_REQUESTS-1:0][31:0] l3_core_req_addr;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag;
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wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_valid;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag;
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wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_ready;
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for (i = 0; i < `L3NUM_REQUESTS; i=i+1) begin
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// Core Request
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assign l3_core_req_valid [i] = (per_cluster_dram_req_read [i] | per_cluster_dram_req_write [i]);
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assign l3_core_req_read [i] = per_cluster_dram_req_read [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
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assign l3_core_req_write [i] = per_cluster_dram_req_write [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
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assign l3_core_req_addr [i] = {per_cluster_dram_req_addr [i], {`LOG2UP(`L2BANK_LINE_SIZE){1'b0}}};
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assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
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assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
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// Core Response
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assign l3_core_rsp_ready [i] = per_cluster_dram_rsp_ready[i];
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// Cache Fill Response
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assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i];
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assign per_cluster_dram_rsp_data [i] = l3_core_rsp_data [i];
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assign per_cluster_dram_rsp_tag [i] = l3_core_rsp_tag [i];
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end
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VX_cache #(
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.CACHE_SIZE (`L3CACHE_SIZE),
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.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
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.NUM_BANKS (`L3NUM_BANKS),
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.WORD_SIZE (`L3WORD_SIZE),
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.NUM_REQUESTS (`L3NUM_REQUESTS),
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.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
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.FUNC_ID (`L2FUNC_ID),
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.REQQ_SIZE (`L3REQQ_SIZE),
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.MRVQ_SIZE (`L3MRVQ_SIZE),
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.DFPQ_SIZE (`L3DFPQ_SIZE),
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.SNRQ_SIZE (`L3SNRQ_SIZE),
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.CWBQ_SIZE (`L3CWBQ_SIZE),
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.DWBQ_SIZE (`L3DWBQ_SIZE),
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.DFQQ_SIZE (`L3DFQQ_SIZE),
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.LLVQ_SIZE (`L3LLVQ_SIZE),
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.FFSQ_SIZE (`L3FFSQ_SIZE),
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.PRFQ_SIZE (`L3PRFQ_SIZE),
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.PRFQ_STRIDE (`L3PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
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.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH)
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) gpu_l3cache (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (l3_core_req_valid),
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.core_req_read (l3_core_req_read),
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.core_req_write (l3_core_req_write),
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.core_req_addr (l3_core_req_addr),
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.core_req_data (l3_core_req_data),
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.core_req_tag (l3_core_req_tag),
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.core_req_ready (l3_core_req_ready),
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// Core response
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.core_rsp_valid (l3_core_rsp_valid),
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.core_rsp_data (l3_core_rsp_data),
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.core_rsp_tag (l3_core_rsp_tag),
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.core_rsp_ready (& l3_core_rsp_ready),
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// DRAM request
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.dram_req_write (dram_req_write),
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.dram_req_read (dram_req_read),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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// DRAM response
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_ready (dram_rsp_ready),
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// Snoop request
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.snp_req_valid (llc_snp_req_valid),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_ready (llc_snp_req_ready),
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// Snoop forwarding
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.snp_fwd_valid (snp_fwd_valid),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_ready (& per_cluster_snp_fwd_ready)
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);
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end
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endmodule |