70 lines
2.6 KiB
Verilog
70 lines
2.6 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_io_arb (
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input wire clk,
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input wire reset,
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// bus select
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input wire select_io_rsp,
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// input requets
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VX_csr_req_if csr_core_req_if,
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VX_csr_io_req_if csr_io_req_if,
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// output request
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VX_csr_pipe_req_if csr_pipe_req_if,
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// input response
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VX_commit_if csr_pipe_rsp_if,
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// outputs responses
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VX_commit_if csr_commit_if,
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VX_csr_io_rsp_if csr_io_rsp_if
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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wire [31:0] csr_core_req_mask = csr_core_req_if.rs2_is_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
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// requests
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assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;
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assign csr_pipe_req_if.wid = csr_core_req_if.wid;
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assign csr_pipe_req_if.tmask = csr_core_req_if.tmask;
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assign csr_pipe_req_if.PC = csr_core_req_if.PC;
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assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
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assign csr_pipe_req_if.csr_addr = csr_core_req_if.valid ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
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assign csr_pipe_req_if.csr_mask = csr_core_req_if.valid ? csr_core_req_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
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assign csr_pipe_req_if.rd = csr_core_req_if.rd;
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assign csr_pipe_req_if.wb = csr_core_req_if.wb;
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assign csr_pipe_req_if.is_io = !csr_core_req_if.valid;
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// core always takes priority over IO bus
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assign csr_core_req_if.ready = csr_pipe_req_if.ready;
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assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid;
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// responses
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wire csr_io_rsp_ready;
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VX_skid_buffer #(
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.DATAW (32)
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) csr_io_out_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (csr_pipe_rsp_if.valid & select_io_rsp),
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.data_in (csr_pipe_rsp_if.data[0]),
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.ready_in (csr_io_rsp_ready),
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.valid_out (csr_io_rsp_if.valid),
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.data_out (csr_io_rsp_if.data),
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.ready_out (csr_io_rsp_if.ready)
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);
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assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp;
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assign csr_commit_if.wid = csr_pipe_rsp_if.wid;
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assign csr_commit_if.tmask = csr_pipe_rsp_if.tmask;
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assign csr_commit_if.PC = csr_pipe_rsp_if.PC;
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assign csr_commit_if.rd = csr_pipe_rsp_if.rd;
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assign csr_commit_if.wb = csr_pipe_rsp_if.wb;
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assign csr_commit_if.data = csr_pipe_rsp_if.data;
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assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready;
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endmodule |