119 lines
3.1 KiB
Verilog
119 lines
3.1 KiB
Verilog
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`include "../VX_define.v"
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// `define NUM_WORDS_PER_BLOCK 4
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module VX_d_cache_encapsulate (
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clk,
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rst,
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i_p_initial_request,
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i_p_addr,
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i_p_writedata,
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i_p_read_or_write,
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i_p_valid,
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o_p_readdata,
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o_p_readdata_valid,
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o_p_waitrequest,
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o_m_addr,
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o_m_writedata,
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o_m_read_or_write,
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o_m_valid,
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i_m_readdata,
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i_m_ready
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);
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parameter NUMBER_BANKS = 8;
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//parameter cache_entry = 9;
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input wire clk, rst;
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input wire i_p_valid[`NT_M1:0];
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input wire [31:0] i_p_addr[`NT_M1:0];
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input wire i_p_initial_request;
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input wire [31:0] i_p_writedata[`NT_M1:0];
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input wire i_p_read_or_write;
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input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
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input wire i_m_ready;
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output reg [31:0] o_p_readdata[`NT_M1:0];
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output reg o_p_readdata_valid[`NT_M1:0] ;
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output reg o_p_waitrequest;
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output reg [31:0] o_m_addr;
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output reg o_m_valid;
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output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
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output reg o_m_read_or_write;
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// Inter
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wire [`NT_M1:0] i_p_valid_inter;
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wire [`NT_M1:0][31:0] i_p_addr_inter;
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wire [`NT_M1:0][31:0] i_p_writedata_inter;
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reg [`NT_M1:0][31:0] o_p_readdata_inter;
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reg [`NT_M1:0] o_p_readdata_valid_inter;
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reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter;
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wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
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genvar curr_thraed;
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for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin
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assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed];
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assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed];
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assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed];
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assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed];
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assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed];
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end
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genvar curr_bank;
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genvar curr_word;
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for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin
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for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
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assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word];
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assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
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end
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end
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VX_d_cache dcache(
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.clk (clk),
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.rst (rst),
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.i_p_valid (i_p_valid_inter),
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.i_p_addr (i_p_addr_inter),
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.i_p_initial_request(i_p_initial_request),
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.i_p_writedata (i_p_writedata_inter),
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.i_p_read_or_write (i_p_read_or_write),
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.o_p_readdata (o_p_readdata_inter),
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.o_p_readdata_valid (o_p_readdata_valid_inter),
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.o_p_waitrequest (o_p_waitrequest),
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.o_m_addr (o_m_addr),
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.o_m_valid (o_m_valid),
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.o_m_writedata (o_m_writedata_inter),
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.o_m_read_or_write (o_m_read_or_write),
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.i_m_readdata (i_m_readdata_inter),
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.i_m_ready (i_m_ready)
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);
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endmodule
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