48 lines
1.9 KiB
C++
48 lines
1.9 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table internal header
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//
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// Internal details; most calling programs do not need this header
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#ifndef _Vcache_simX__Syms_H_
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#define _Vcache_simX__Syms_H_
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#include "verilated.h"
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// INCLUDE MODULE CLASSES
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#include "Vcache_simX.h"
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#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
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#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
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#include "Vcache_simX_VX_dcache_request_inter.h"
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#include "Vcache_simX_VX_Cache_Bank__pi8.h"
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// SYMS CLASS
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class Vcache_simX__Syms : public VerilatedSyms {
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public:
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// LOCAL STATE
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const char* __Vm_namep;
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bool __Vm_activity; ///< Used by trace routines to determine change occurred
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bool __Vm_didInit;
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// SUBCELL STATE
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Vcache_simX* TOPp;
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Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
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Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
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Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
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Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
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Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
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Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
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Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
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// CREATORS
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Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
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~Vcache_simX__Syms() {}
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// METHODS
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inline const char* name() { return __Vm_namep; }
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inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
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} VL_ATTR_ALIGNED(64);
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#endif // guard
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