23 lines
571 B
Verilog
23 lines
571 B
Verilog
`ifndef VX_MEM_REQ_IF
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`define VX_MEM_REQ_IF
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`include "../cache/VX_cache_define.vh"
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interface VX_mem_req_if #(
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parameter MEM_LINE_WIDTH = 1,
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parameter MEM_ADDR_WIDTH = 1,
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parameter MEM_TAG_WIDTH = 1,
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parameter MEM_LINE_SIZE = MEM_LINE_WIDTH / 8
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) ();
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wire valid;
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wire rw;
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wire [MEM_LINE_SIZE-1:0] byteen;
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wire [MEM_ADDR_WIDTH-1:0] addr;
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wire [MEM_LINE_WIDTH-1:0] data;
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wire [MEM_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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`endif |