129 lines
3.3 KiB
Systemverilog
129 lines
3.3 KiB
Systemverilog
// Copyright 2024 blaise
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// A stream elastic buffer operates at full-bandwidth where push and pop can happen simultaneously
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// It has the following benefits:
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// + full-bandwidth throughput
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// + ready_in and ready_out are decoupled
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// + data_out can be fully registered
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// It has the following limitations:
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// - requires two registers for storage
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_stream_buffer #(
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parameter DATAW = 1,
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parameter OUT_REG = 0,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU != 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign ready_in = ready_out;
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assign valid_out = valid_in;
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assign data_out = data_in;
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] data_out_r;
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reg [DATAW-1:0] buffer;
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reg valid_out_r;
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reg use_buffer;
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wire push = valid_in && ready_in;
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wire stall_out = valid_out_r && ~ready_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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use_buffer <= 0;
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end else begin
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if (ready_out) begin
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use_buffer <= 0;
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end else if (valid_in && valid_out) begin
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use_buffer <= 1;
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end
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if (~stall_out) begin
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valid_out_r <= valid_in || use_buffer;
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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buffer <= data_in;
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end
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if (~stall_out) begin
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data_out_r <= use_buffer ? buffer : data_in;
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end
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end
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assign ready_in = ~use_buffer;
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assign valid_out = valid_out_r;
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assign data_out = data_out_r;
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end else begin
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reg [1:0][DATAW-1:0] shift_reg;
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reg valid_out_r, ready_in_r, rd_ptr_r;
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wire push = valid_in && ready_in;
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wire pop = valid_out_r && ready_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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ready_in_r <= 1;
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rd_ptr_r <= 1;
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end else begin
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if (push) begin
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if (!pop) begin
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ready_in_r <= rd_ptr_r;
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valid_out_r <= 1;
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end
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end else if (pop) begin
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ready_in_r <= 1;
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valid_out_r <= rd_ptr_r;
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end
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rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
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end
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end
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always @(posedge clk) begin
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if (push) begin
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shift_reg[1] <= shift_reg[0];
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shift_reg[0] <= data_in;
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end
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end
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assign ready_in = ready_in_r;
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assign valid_out = valid_out_r;
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assign data_out = shift_reg[rd_ptr_r];
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end
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end
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endmodule
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`TRACING_ON
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