279 lines
10 KiB
Verilog
279 lines
10 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_unit # (
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_mem_unit
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input wire clk,
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input wire reset,
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// Core <-> Dcache
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VX_cache_core_req_if core_dcache_req_if,
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VX_cache_core_rsp_if core_dcache_rsp_if,
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// DRAM <-> Dcache
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VX_cache_dram_req_if dcache_dram_req_if,
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VX_cache_dram_rsp_if dcache_dram_rsp_if,
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VX_cache_snp_req_if dcache_snp_req_if,
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VX_cache_snp_rsp_if dcache_snp_rsp_if,
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// Core <-> Icache
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VX_cache_core_req_if core_icache_req_if,
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VX_cache_core_rsp_if core_icache_rsp_if,
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// DRAM <-> Icache
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VX_cache_dram_req_if icache_dram_req_if,
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VX_cache_dram_rsp_if icache_dram_rsp_if
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);
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VX_cache_core_req_if #(
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.NUM_REQUESTS (`DNUM_REQUESTS),
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.WORD_SIZE (`DWORD_SIZE),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
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) core_dcache_req_qual_if(), core_smem_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS (`DNUM_REQUESTS),
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.WORD_SIZE (`DWORD_SIZE),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
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) core_dcache_rsp_qual_if(), core_smem_rsp_if();
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// select shared memory bus
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wire is_smem_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
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&& ({core_dcache_req_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SCACHE_SIZE));
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wire smem_req_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0;
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wire smem_rsp_select = (| core_smem_rsp_if.valid);
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VX_dcache_arb dcache_smem_arb (
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.core_req_in_if (core_dcache_req_if),
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.core_req_out0_if (core_dcache_req_qual_if),
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.core_req_out1_if (core_smem_req_if),
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.core_rsp_in0_if (core_dcache_rsp_qual_if),
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.core_rsp_in1_if (core_smem_rsp_if),
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.core_rsp_out_if (core_dcache_rsp_if),
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.select_req (smem_req_select),
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.select_rsp (smem_rsp_select)
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);
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VX_cache #(
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.CACHE_ID (`SCACHE_ID),
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.CACHE_SIZE (`SCACHE_SIZE),
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.BANK_LINE_SIZE (`SBANK_LINE_SIZE),
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.NUM_BANKS (`SNUM_BANKS),
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.WORD_SIZE (`SWORD_SIZE),
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.NUM_REQUESTS (`SNUM_REQUESTS),
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.CREQ_SIZE (`SCREQ_SIZE),
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.MSHR_SIZE (8),
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.DRFQ_SIZE (1),
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.SNRQ_SIZE (1),
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.CWBQ_SIZE (`SCWBQ_SIZE),
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.DREQ_SIZE (1),
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.SNPQ_SIZE (1),
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.DRAM_ENABLE (0),
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.FLUSH_ENABLE (0),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
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.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
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) smem (
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`SCOPE_BIND_VX_mem_unit_smem
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (core_smem_req_if.valid),
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.core_req_rw (core_smem_req_if.rw),
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.core_req_byteen (core_smem_req_if.byteen),
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.core_req_addr (core_smem_req_if.addr),
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.core_req_data (core_smem_req_if.data),
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.core_req_tag (core_smem_req_if.tag),
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.core_req_ready (core_smem_req_if.ready),
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// Core response
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.core_rsp_valid (core_smem_rsp_if.valid),
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.core_rsp_data (core_smem_rsp_if.data),
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.core_rsp_tag (core_smem_rsp_if.tag),
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.core_rsp_ready (core_smem_rsp_if.ready),
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// DRAM request
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`UNUSED_PIN (dram_req_valid),
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`UNUSED_PIN (dram_req_rw),
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`UNUSED_PIN (dram_req_byteen),
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`UNUSED_PIN (dram_req_addr),
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`UNUSED_PIN (dram_req_data),
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`UNUSED_PIN (dram_req_tag),
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.dram_req_ready (1'b0),
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// DRAM response
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.dram_rsp_valid (0),
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.dram_rsp_data (0),
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.dram_rsp_tag (0),
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`UNUSED_PIN (dram_rsp_ready),
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// Snoop request
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.snp_req_valid (1'b0),
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.snp_req_addr (0),
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.snp_req_invalidate (0),
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.snp_req_tag (0),
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`UNUSED_PIN (snp_req_ready),
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// Snoop response
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`UNUSED_PIN (snp_rsp_valid),
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`UNUSED_PIN (snp_rsp_tag),
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.snp_rsp_ready (1'b0),
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// Miss status
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`UNUSED_PIN (miss_vec)
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);
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VX_cache #(
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.CACHE_ID (`DCACHE_ID),
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.CACHE_SIZE (`DCACHE_SIZE),
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.BANK_LINE_SIZE (`DBANK_LINE_SIZE),
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.NUM_BANKS (`DNUM_BANKS),
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.WORD_SIZE (`DWORD_SIZE),
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.NUM_REQUESTS (`DNUM_REQUESTS),
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.CREQ_SIZE (`DCREQ_SIZE),
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.MSHR_SIZE (`DMSHR_SIZE),
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.DRFQ_SIZE (`DDRFQ_SIZE),
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.SNRQ_SIZE (`DSNRQ_SIZE),
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.CWBQ_SIZE (`DCWBQ_SIZE),
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.DREQ_SIZE (`DDREQ_SIZE),
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.SNPQ_SIZE (`DSNPQ_SIZE),
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.DRAM_ENABLE (1),
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.FLUSH_ENABLE (1),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
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.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
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.SNP_TAG_WIDTH (`DSNP_TAG_WIDTH)
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) dcache (
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`SCOPE_BIND_VX_mem_unit_dcache
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.clk (clk),
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.reset (reset),
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// Core req
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.core_req_valid (core_dcache_req_qual_if.valid),
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.core_req_rw (core_dcache_req_qual_if.rw),
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.core_req_byteen (core_dcache_req_qual_if.byteen),
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.core_req_addr (core_dcache_req_qual_if.addr),
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.core_req_data (core_dcache_req_qual_if.data),
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.core_req_tag (core_dcache_req_qual_if.tag),
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.core_req_ready (core_dcache_req_qual_if.ready),
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// Core response
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.core_rsp_valid (core_dcache_rsp_qual_if.valid),
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.core_rsp_data (core_dcache_rsp_qual_if.data),
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.core_rsp_tag (core_dcache_rsp_qual_if.tag),
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.core_rsp_ready (core_dcache_rsp_qual_if.ready),
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// DRAM request
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.dram_req_valid (dcache_dram_req_if.valid),
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.dram_req_rw (dcache_dram_req_if.rw),
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.dram_req_byteen (dcache_dram_req_if.byteen),
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.dram_req_addr (dcache_dram_req_if.addr),
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.dram_req_data (dcache_dram_req_if.data),
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.dram_req_tag (dcache_dram_req_if.tag),
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.dram_req_ready (dcache_dram_req_if.ready),
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// DRAM response
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.dram_rsp_valid (dcache_dram_rsp_if.valid),
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.dram_rsp_data (dcache_dram_rsp_if.data),
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.dram_rsp_tag (dcache_dram_rsp_if.tag),
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.dram_rsp_ready (dcache_dram_rsp_if.ready),
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// Snoop request
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.snp_req_valid (dcache_snp_req_if.valid),
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.snp_req_addr (dcache_snp_req_if.addr),
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.snp_req_invalidate (dcache_snp_req_if.invalidate),
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.snp_req_tag (dcache_snp_req_if.tag),
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.snp_req_ready (dcache_snp_req_if.ready),
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// Snoop response
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.snp_rsp_valid (dcache_snp_rsp_if.valid),
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.snp_rsp_tag (dcache_snp_rsp_if.tag),
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.snp_rsp_ready (dcache_snp_rsp_if.ready),
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// Miss status
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`UNUSED_PIN (miss_vec)
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);
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VX_cache #(
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.CACHE_ID (`ICACHE_ID),
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.CACHE_SIZE (`ICACHE_SIZE),
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.BANK_LINE_SIZE (`IBANK_LINE_SIZE),
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.NUM_BANKS (`INUM_BANKS),
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.WORD_SIZE (`IWORD_SIZE),
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.NUM_REQUESTS (`INUM_REQUESTS),
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.CREQ_SIZE (`ICREQ_SIZE),
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.MSHR_SIZE (`IMSHR_SIZE),
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.DRFQ_SIZE (`IDRFQ_SIZE),
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.SNRQ_SIZE (1),
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.CWBQ_SIZE (`ICWBQ_SIZE),
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.DREQ_SIZE (`IDREQ_SIZE),
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.SNPQ_SIZE (1),
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.DRAM_ENABLE (1),
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.FLUSH_ENABLE (0),
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.WRITE_ENABLE (0),
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.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
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.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
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) icache (
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`SCOPE_BIND_VX_mem_unit_icache
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (core_icache_req_if.valid),
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.core_req_rw (core_icache_req_if.rw),
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.core_req_byteen (core_icache_req_if.byteen),
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.core_req_addr (core_icache_req_if.addr),
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.core_req_data (core_icache_req_if.data),
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.core_req_tag (core_icache_req_if.tag),
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.core_req_ready (core_icache_req_if.ready),
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// Core response
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.core_rsp_valid (core_icache_rsp_if.valid),
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.core_rsp_data (core_icache_rsp_if.data),
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.core_rsp_tag (core_icache_rsp_if.tag),
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.core_rsp_ready (core_icache_rsp_if.ready),
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// DRAM Req
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.dram_req_valid (icache_dram_req_if.valid),
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.dram_req_rw (icache_dram_req_if.rw),
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.dram_req_byteen (icache_dram_req_if.byteen),
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.dram_req_addr (icache_dram_req_if.addr),
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.dram_req_data (icache_dram_req_if.data),
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.dram_req_tag (icache_dram_req_if.tag),
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.dram_req_ready (icache_dram_req_if.ready),
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// DRAM response
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.dram_rsp_valid (icache_dram_rsp_if.valid),
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.dram_rsp_data (icache_dram_rsp_if.data),
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.dram_rsp_tag (icache_dram_rsp_if.tag),
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.dram_rsp_ready (icache_dram_rsp_if.ready),
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// Snoop request
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.snp_req_valid (1'b0),
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.snp_req_addr (0),
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.snp_req_invalidate (1'b0),
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.snp_req_tag (0),
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`UNUSED_PIN (snp_req_ready),
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// Snoop response
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`UNUSED_PIN (snp_rsp_valid),
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`UNUSED_PIN (snp_rsp_tag),
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.snp_rsp_ready (1'b0),
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// Miss status
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`UNUSED_PIN (miss_vec)
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);
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endmodule
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