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b85391389b0bb9816a47573ae173e5aa3d1fc2d7
vortex/hw/rtl
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Blaise Tine b85391389b rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
..
cache
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
fp_cores
tabs cleanup
2020-11-28 17:08:01 -05:00
interfaces
tabs cleanup
2020-11-28 17:08:01 -05:00
libs
tabs cleanup
2020-11-28 17:08:01 -05:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
VX_alu_unit.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_cluster.v
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
VX_commit.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_config.vh
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
VX_core.v
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_csr_arb.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_csr_data.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_csr_io_arb.v
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_csr_unit.v
fixed scoreboard stall
2020-11-28 03:14:20 -05:00
VX_dcache_arb.v
pipeline refactoring
2020-07-19 05:03:47 -04:00
VX_decode.v
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
VX_define.vh
scope minor fix
2020-11-22 11:51:46 -08:00
VX_execute.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_fetch.v
scope fixes
2020-10-13 08:44:55 -07:00
VX_fpu_unit.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_gpr_bypass.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_gpr_ram.v
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_gpr_stage.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_gpu_unit.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_ibuffer.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_icache_stage.v
fixed l3cache hang using memory arbiter in afu
2020-11-15 06:36:32 -08:00
VX_instr_demux.v
synchronous reset network optimization: only reset register when required
2020-11-11 20:54:54 -08:00
VX_io_arb.v
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_ipdom_stack.v
vlsim fix, verilator fst trace, use ram optimization
2020-10-25 16:40:50 -07:00
VX_issue.v
pipeline optimization: fixed GPR fanout delay to execute units
2020-11-07 02:01:21 -08:00
VX_lsu_unit.v
build warnings clean
2020-11-28 14:59:13 -05:00
VX_mem_arb.v
fixed l3cache hang using memory arbiter in afu
2020-11-15 06:36:32 -08:00
VX_mem_unit.v
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
VX_mul_unit.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_opd_collect.v
pipeline optimization: fixed GPR fanout delay to execute units
2020-11-07 02:01:21 -08:00
VX_pipeline.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_platform.vh
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_print_instr.vh
optimize warp_sched
2020-08-24 05:36:00 -07:00
VX_scope.vh
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_scoreboard.v
fixed scoreboard stall
2020-11-28 03:14:20 -05:00
VX_types.vh
scope refactoring: adding modules definitions to VCD trace
2020-10-12 23:26:02 -04:00
VX_warp_sched.v
fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
2020-11-17 00:27:24 -08:00
VX_writeback.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00