377 lines
16 KiB
Systemverilog
377 lines
16 KiB
Systemverilog
`ifndef VX_SCOPE
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`define VX_SCOPE
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`ifdef SCOPE
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`define SCOPE_SIGNALS_DATA_LIST \
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scope_dram_req_addr, \
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scope_dram_req_rw, \
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scope_dram_req_byteen, \
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scope_dram_req_data, \
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scope_dram_req_tag, \
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scope_dram_rsp_data, \
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scope_dram_rsp_tag, \
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scope_snp_req_addr, \
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scope_snp_req_invalidate, \
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scope_snp_req_tag, \
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scope_snp_rsp_tag, \
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scope_icache_req_warp_num, \
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scope_icache_req_addr, \
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scope_icache_req_tag, \
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scope_icache_rsp_data, \
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scope_icache_rsp_tag, \
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scope_dcache_req_warp_num, \
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scope_dcache_req_curr_PC, \
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scope_dcache_req_addr, \
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scope_dcache_req_rw, \
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scope_dcache_req_byteen, \
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scope_dcache_req_data, \
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scope_dcache_req_tag, \
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scope_dcache_rsp_data, \
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scope_dcache_rsp_tag, \
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scope_decode_warp_num, \
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scope_decode_curr_PC, \
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scope_decode_is_jal, \
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scope_decode_rs1, \
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scope_decode_rs2, \
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scope_execute_warp_num, \
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scope_execute_curr_PC, \
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scope_execute_rd, \
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scope_execute_a, \
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scope_execute_b, \
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scope_writeback_warp_num, \
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scope_writeback_curr_PC, \
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scope_writeback_wb, \
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scope_writeback_rd, \
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scope_writeback_data, \
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scope_bank_addr_st0, \
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scope_bank_addr_st1, \
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scope_bank_addr_st2, \
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scope_bank_is_mrvq_st1, \
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scope_bank_miss_st1, \
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scope_bank_dirty_st1, \
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scope_bank_force_miss_st1,
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`define SCOPE_SIGNALS_UPD_LIST \
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scope_dram_req_valid, \
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scope_dram_req_ready, \
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scope_dram_rsp_valid, \
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scope_dram_rsp_ready, \
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scope_snp_req_valid, \
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scope_snp_req_ready, \
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scope_snp_rsp_valid, \
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scope_snp_rsp_ready, \
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scope_icache_req_valid, \
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scope_icache_req_ready, \
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scope_icache_rsp_valid, \
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scope_icache_rsp_ready, \
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scope_dcache_req_valid, \
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scope_dcache_req_ready, \
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scope_dcache_rsp_valid, \
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scope_dcache_rsp_ready, \
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scope_decode_valid, \
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scope_execute_valid, \
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scope_writeback_valid, \
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scope_schedule_delay, \
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scope_memory_delay, \
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scope_exec_delay, \
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scope_gpr_stage_delay, \
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scope_busy, \
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scope_bank_valid_st0, \
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scope_bank_valid_st1, \
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scope_bank_valid_st2, \
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scope_bank_stall_pipe
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`define SCOPE_SIGNALS_DECL \
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wire scope_dram_req_valid; \
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wire [31:0] scope_dram_req_addr; \
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wire scope_dram_req_rw; \
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wire [15:0] scope_dram_req_byteen; \
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wire [127:0] scope_dram_req_data; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
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wire scope_dram_req_ready; \
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wire scope_dram_rsp_valid; \
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wire [127:0] scope_dram_rsp_data; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
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wire scope_dram_rsp_ready; \
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wire scope_snp_req_valid; \
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wire [31:0] scope_snp_req_addr; \
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wire scope_snp_req_invalidate; \
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wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
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wire scope_snp_req_ready; \
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wire scope_snp_rsp_valid; \
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wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
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wire scope_icache_req_valid; \
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wire [`NW_BITS-1:0] scope_icache_req_warp_num; \
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wire [31:0] scope_icache_req_addr; \
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wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
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wire scope_icache_req_ready; \
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wire scope_icache_rsp_valid; \
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wire [31:0] scope_icache_rsp_data; \
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wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
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wire scope_icache_rsp_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
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wire [`NW_BITS-1:0] scope_dcache_req_warp_num; \
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wire [31:0] scope_dcache_req_curr_PC; \
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wire [63:0] scope_dcache_req_addr; \
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wire scope_dcache_req_rw; \
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wire [7:0] scope_dcache_req_byteen; \
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wire [63:0] scope_dcache_req_data; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
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wire scope_dcache_req_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
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wire [63:0] scope_dcache_rsp_data; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
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wire scope_dcache_rsp_ready; \
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wire scope_busy; \
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wire scope_snp_rsp_ready; \
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wire scope_schedule_delay; \
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wire scope_memory_delay; \
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wire scope_exec_delay; \
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wire scope_gpr_stage_delay; \
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wire [`NUM_THREADS-1:0] scope_decode_valid; \
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wire [`NW_BITS-1:0] scope_decode_warp_num; \
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wire [31:0] scope_decode_curr_PC; \
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wire scope_decode_is_jal; \
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wire [4:0] scope_decode_rs1; \
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wire [4:0] scope_decode_rs2; \
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wire [`NUM_THREADS-1:0] scope_execute_valid; \
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wire [`NW_BITS-1:0] scope_execute_warp_num; \
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wire [31:0] scope_execute_curr_PC; \
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wire [4:0] scope_execute_rd; \
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wire [63:0] scope_execute_a; \
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wire [63:0] scope_execute_b; \
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wire [`NUM_THREADS-1:0] scope_writeback_valid; \
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wire [`NW_BITS-1:0] scope_writeback_warp_num; \
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wire [31:0] scope_writeback_curr_PC; \
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wire [1:0] scope_writeback_wb; \
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wire [4:0] scope_writeback_rd; \
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wire [63:0] scope_writeback_data; \
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wire scope_bank_valid_st0; \
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wire scope_bank_valid_st1; \
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wire scope_bank_valid_st2; \
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wire [31:0] scope_bank_addr_st0; \
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wire [31:0] scope_bank_addr_st1; \
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wire [31:0] scope_bank_addr_st2; \
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wire scope_bank_is_mrvq_st1; \
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wire scope_bank_miss_st1; \
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wire scope_bank_dirty_st1; \
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wire scope_bank_force_miss_st1; \
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wire scope_bank_stall_pipe;
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`define SCOPE_SIGNALS_ISTAGE_IO \
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output wire scope_icache_req_valid, \
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output wire [`NW_BITS-1:0] scope_icache_req_warp_num, \
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output wire [31:0] scope_icache_req_addr, \
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output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
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output wire scope_icache_req_ready, \
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output wire scope_icache_rsp_valid, \
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output wire [31:0] scope_icache_rsp_data, \
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output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
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output wire scope_icache_rsp_ready,
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`define SCOPE_SIGNALS_LSU_IO \
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output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
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output wire [`NW_BITS-1:0] scope_dcache_req_warp_num, \
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output wire [31:0] scope_dcache_req_curr_PC, \
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output wire [63:0] scope_dcache_req_addr, \
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output wire scope_dcache_req_rw, \
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output wire [7:0] scope_dcache_req_byteen, \
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output wire [63:0] scope_dcache_req_data, \
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output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
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output wire scope_dcache_req_ready, \
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output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
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output wire [63:0] scope_dcache_rsp_data, \
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output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
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output wire scope_dcache_rsp_ready,
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`define SCOPE_SIGNALS_CORE_IO \
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`define SCOPE_SIGNALS_CACHE_IO \
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output wire scope_bank_valid_st0, \
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output wire scope_bank_valid_st1, \
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output wire scope_bank_valid_st2, \
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output wire [31:0] scope_bank_addr_st0, \
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output wire [31:0] scope_bank_addr_st1, \
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output wire [31:0] scope_bank_addr_st2, \
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output wire scope_bank_is_mrvq_st1, \
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output wire scope_bank_miss_st1, \
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output wire scope_bank_dirty_st1, \
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output wire scope_bank_force_miss_st1, \
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output wire scope_bank_stall_pipe,
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`define SCOPE_SIGNALS_PIPELINE_IO \
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output wire scope_busy, \
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output wire scope_schedule_delay, \
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output wire scope_memory_delay, \
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output wire scope_exec_delay, \
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output wire scope_gpr_stage_delay,
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`define SCOPE_SIGNALS_BE_IO \
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output wire [`NUM_THREADS-1:0] scope_decode_valid, \
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output wire [`NW_BITS-1:0] scope_decode_warp_num, \
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output wire [31:0] scope_decode_curr_PC, \
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output wire scope_decode_is_jal, \
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output wire [4:0] scope_decode_rs1, \
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output wire [4:0] scope_decode_rs2, \
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output wire [`NUM_THREADS-1:0] scope_execute_valid, \
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output wire [`NW_BITS-1:0] scope_execute_warp_num, \
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output wire [31:0] scope_execute_curr_PC, \
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output wire [4:0] scope_execute_rd, \
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output wire [63:0] scope_execute_a, \
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output wire [63:0] scope_execute_b, \
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output wire [`NUM_THREADS-1:0] scope_writeback_valid, \
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output wire [`NW_BITS-1:0] scope_writeback_warp_num, \
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output wire [31:0] scope_writeback_curr_PC, \
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output wire [1:0] scope_writeback_wb, \
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output wire [4:0] scope_writeback_rd, \
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output wire [63:0] scope_writeback_data,
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`define SCOPE_SIGNALS_ISTAGE_BIND \
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.scope_icache_req_valid (scope_icache_req_valid), \
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.scope_icache_req_warp_num (scope_icache_req_warp_num), \
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.scope_icache_req_addr (scope_icache_req_addr), \
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.scope_icache_req_tag (scope_icache_req_tag), \
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.scope_icache_req_ready (scope_icache_req_ready), \
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.scope_icache_rsp_valid (scope_icache_rsp_valid), \
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.scope_icache_rsp_data (scope_icache_rsp_data), \
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.scope_icache_rsp_tag (scope_icache_rsp_tag), \
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.scope_icache_rsp_ready (scope_icache_rsp_ready),
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`define SCOPE_SIGNALS_LSU_BIND \
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.scope_dcache_req_valid (scope_dcache_req_valid), \
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.scope_dcache_req_warp_num (scope_dcache_req_warp_num), \
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.scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \
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.scope_dcache_req_addr (scope_dcache_req_addr), \
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.scope_dcache_req_rw (scope_dcache_req_rw), \
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.scope_dcache_req_byteen(scope_dcache_req_byteen), \
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.scope_dcache_req_data (scope_dcache_req_data), \
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.scope_dcache_req_tag (scope_dcache_req_tag), \
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.scope_dcache_req_ready (scope_dcache_req_ready), \
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.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
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.scope_dcache_rsp_data (scope_dcache_rsp_data), \
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.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
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.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
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`define SCOPE_SIGNALS_CORE_BIND \
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`define SCOPE_SIGNALS_CACHE_BIND \
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.scope_bank_valid_st0 (scope_bank_valid_st0), \
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.scope_bank_valid_st1 (scope_bank_valid_st1), \
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.scope_bank_valid_st2 (scope_bank_valid_st2), \
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.scope_bank_addr_st0 (scope_bank_addr_st0), \
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.scope_bank_addr_st1 (scope_bank_addr_st1), \
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.scope_bank_addr_st2 (scope_bank_addr_st2), \
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.scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \
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.scope_bank_miss_st1 (scope_bank_miss_st1), \
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.scope_bank_dirty_st1 (scope_bank_dirty_st1), \
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.scope_bank_force_miss_st1 (scope_bank_force_miss_st1), \
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.scope_bank_stall_pipe (scope_bank_stall_pipe),
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`define SCOPE_SIGNALS_CACHE_UNBIND \
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/* verilator lint_off PINCONNECTEMPTY */ \
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.scope_bank_valid_st0 (), \
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.scope_bank_valid_st1 (), \
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.scope_bank_valid_st2 (), \
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.scope_bank_addr_st0 (), \
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.scope_bank_addr_st1 (), \
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.scope_bank_addr_st2 (), \
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.scope_bank_is_mrvq_st1 (), \
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.scope_bank_miss_st1 (), \
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.scope_bank_dirty_st1 (), \
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.scope_bank_force_miss_st1 (), \
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.scope_bank_stall_pipe (), \
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/* verilator lint_on PINCONNECTEMPTY */
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`define SCOPE_SIGNALS_CACHE_BANK_SELECT \
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/* verilator lint_off UNUSED */ \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st0; \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st2; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st0; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st1; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st2; \
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wire [NUM_BANKS-1:0] scope_per_bank_is_mrvq_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_miss_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_dirty_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_force_miss_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_stall_pipe; \
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/* verilator lint_on UNUSED */ \
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assign scope_bank_valid_st0 = scope_per_bank_valid_st0[0]; \
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assign scope_bank_valid_st1 = scope_per_bank_valid_st1[0]; \
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assign scope_bank_valid_st2 = scope_per_bank_valid_st2[0]; \
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assign scope_bank_addr_st0 = scope_per_bank_addr_st0[0]; \
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assign scope_bank_addr_st1 = scope_per_bank_addr_st1[0]; \
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assign scope_bank_addr_st2 = scope_per_bank_addr_st2[0]; \
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assign scope_bank_is_mrvq_st1 = scope_per_bank_is_mrvq_st1[0]; \
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assign scope_bank_miss_st1 = scope_per_bank_miss_st1[0]; \
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assign scope_bank_dirty_st1 = scope_per_bank_dirty_st1[0]; \
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assign scope_bank_force_miss_st1 = scope_per_bank_force_miss_st1[0]; \
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assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
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`define SCOPE_SIGNALS_CACHE_BANK_BIND \
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.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
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.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
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.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
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.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
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.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
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.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
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.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
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.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
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.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
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.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
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.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
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`define SCOPE_SIGNALS_PIPELINE_BIND \
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.scope_busy (scope_busy), \
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.scope_schedule_delay (scope_schedule_delay), \
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.scope_memory_delay (scope_memory_delay), \
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.scope_exec_delay (scope_exec_delay), \
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.scope_gpr_stage_delay (scope_gpr_stage_delay),
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`define SCOPE_SIGNALS_BE_BIND \
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.scope_decode_valid (scope_decode_valid), \
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.scope_decode_warp_num (scope_decode_warp_num), \
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.scope_decode_curr_PC (scope_decode_curr_PC), \
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.scope_decode_is_jal (scope_decode_is_jal), \
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.scope_decode_rs1 (scope_decode_rs1), \
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.scope_decode_rs2 (scope_decode_rs2), \
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.scope_execute_valid (scope_execute_valid), \
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.scope_execute_warp_num (scope_execute_warp_num), \
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.scope_execute_curr_PC (scope_execute_curr_PC), \
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.scope_execute_rd (scope_execute_rd), \
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.scope_execute_a (scope_execute_a), \
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.scope_execute_b (scope_execute_b), \
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.scope_writeback_valid (scope_writeback_valid), \
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.scope_writeback_warp_num (scope_writeback_warp_num), \
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.scope_writeback_curr_PC(scope_writeback_curr_PC), \
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.scope_writeback_wb (scope_writeback_wb), \
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.scope_writeback_rd (scope_writeback_rd), \
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.scope_writeback_data (scope_writeback_data),
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`define SCOPE_ASSIGN(d,s) assign d = s
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`else
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`define SCOPE_SIGNALS_ISTAGE_IO
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`define SCOPE_SIGNALS_LSU_IO
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`define SCOPE_SIGNALS_CORE_IO
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`define SCOPE_SIGNALS_CACHE_IO
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`define SCOPE_SIGNALS_PIPELINE_IO
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`define SCOPE_SIGNALS_BE_IO
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`define SCOPE_SIGNALS_ISTAGE_BIND
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`define SCOPE_SIGNALS_LSU_BIND
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`define SCOPE_SIGNALS_CORE_BIND
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`define SCOPE_SIGNALS_CACHE_BIND
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`define SCOPE_SIGNALS_PIPELINE_BIND
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`define SCOPE_SIGNALS_BE_BIND
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`define SCOPE_SIGNALS_CACHE_UNBIND
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`define SCOPE_SIGNALS_CACHE_BANK_SELECT
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`define SCOPE_SIGNALS_CACHE_BANK_BIND
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`define SCOPE_ASSIGN(d,s)
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`endif
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// VX_SCOPE
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`endif |