94 lines
3.8 KiB
Markdown
94 lines
3.8 KiB
Markdown
# Vortex Microarchitecture
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### Vortex GPGPU Execution Model
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Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with a single warp issued per cycle.
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- **Threads**
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- Smallest unit of computation
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- Each thread has its own register file (32 int + 32 fp registers)
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- Threads execute in parallel
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- **Warps**
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- A logical clster of threads
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- Each thread in a warp execute the same instruction
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- The PC is shared; maintain thread mask for Writeback
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- Warp's execution is time-multiplexed at log steps
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- Ex. warp 0 executes at cycle 0, warp 1 executes at cycle 1
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### Vortex RISC-V ISA Extension
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- **Thread Mask Control**
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- Control the number of warps to activate during execution
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- `TMC` *count*: activate count threads
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- **Warp Scheduling**
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- Control the number of warps to activate during execution
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- `WSPAWN` *count, addr*: activate count warps and jump to addr location
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- **Control-Flow Divergence**
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- Control threads to activate when a branch diverges
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- `SPLIT` *predicate*: apply 'taken' predicate thread mask adn save 'not-taken' into IPDOM stack
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- `JOIN`: restore 'not-taken' thread mask
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- **Warp Synchronization**
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- `BAR` *id, count*: stall warps entering barrier *id* until count is reached
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### Vortex Pipeline/Datapath
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Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB.
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- **Fetch**
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- Warp Scheduler
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- Track stalled & active warps, resolve branches and barriers, maintain split/join IPDOM stack
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- Instruction Cache
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- Retrieve instruction from cache, issue I-cache requests/responses
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- **Decode**
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- Decode fetched instructions, notify warp scheduler when the following instructions are decoded:
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- Branch, tmc, split/join, wspawn
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- Precompute used_regs mask (needed for Issue stage)
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- **Issue**
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- Scheduling
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- In-order issue (operands/execute unit ready), out-of-order commit
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- IBuffer
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- Store fetched instructions, separate queues per-warp, selects next warp through round-robin scheduling
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- Scoreboard
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- Track in-use registers
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- GPRs (General-Purpose Registers) stage
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- Fetch issued instruction operands and send operands to execute unit
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- **Execute**
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- ALU Unit
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- Single-cycle operations (+,-,>>,<<,&,|,^), Branch instructions (Share ALU resources)
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- MULDIV Unit
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- Multiplier - done in 2 cycles
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- Divider - division and remainder, done in 32 cycles
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- Implements serial alogrithm (Stalls the pipeline)
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- FPU Unit
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- Multi-cycle operations, uses `FPnew` Library on ASIC, uses hard DSPs on FPGA
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- CSR Unit
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- Store constant status registers - device caps, FPU status flags, performance counters
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- Handle external CSR requests (requests from host CPU)
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- LSU Unit
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- Handle load/store operations, issue D-cache requests, handle D-cache responses
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- Commit load responses - saves storage, Scoreboard tracks completion
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- GPGPU Unit
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- Handle GPGPU instructions
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- TMC, WSPAWN, SPLIT, BAR
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- JOIN is handled by Warp Scheduler (upon SPLIT response)
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- **Commit**
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- Commit
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- Update CSR flags, update performance counters
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- Writeback
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- Write result back to GPRs, notify Scoreboard (release in-use register), select candidate instruction (ALU unit has highest priority)
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- **Clustering**
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- Group mulitple cores into clusters (optionally share L2 cache)
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- Group multiple clusters (optionally share L3 cache)
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- Configurable at build time
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- Default configuration:
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- #Clusters = 1
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- #Cores = 4
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- #Warps = 4
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- #Threads = 4
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- **FPGA AFU Interface**
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- Manage CPU-GPU comunication
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- Query devices caps, load kernel instructions and resource buffers, start kernel execution, read destination buffers
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- Local Memory - GPU access to local DRAM
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- Reserved I/O addresses - redirect to host CPU, console output |